• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.730-736
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• 2008

We proposed and implemented new DDC system which overcomes the difficulties including lack of flexibility of modifications of frequency which is the problem of previous frequence oscillator and synchronization. New DDC system can create frequence in two decimal points. Moreover, due to its usage in adjusting to frequence clock which is required by many consumers, laser distance instrument can reduce its error; thus, implementation of system is capable of high precision distance measurement can be performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.31-35
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• 2009

In this paper, tunable 4th order SC(switched capacitor) bandpass ${\sigma}-{\Delta}$(Sigma-Delta) modulator with advanced architecture that can adjust the IF by two coefficient values is proposed for data conversion in the wireless communication. Its architecture can optionally adjust all the 4th order noise transfer function in comparison with the conventional architecture. In order to adjust the IF, the conventional architecture needs the four variable coefficients values, basic clocks and eight clocks. On the other hand, the proposed architecture can adjust the IF by two variable coefficient values and basic clocks only.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.331-334
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• 2004

본 논문에서는 클록의 duty ratio가 변하였을 때, 그 클록의 duty ratio를 $50\%$의 duty ratio로 만들어 주는 Pulse Width Control Loop Circuit을 설계하였다. 기존의 논문에서는 duty ratio를 변화시키기 위해 각 duty ratio 마다 알맞은 제어 전압을 공급해하는 문제점이 있었다. 본 논문은 제어 전압이 변하지 않고 일정한 전압으로도 duty ratio를 변화시킬 수 있게 하여, 제어 전압 변화에 대한 문제점을 해결하였다. 설계, 시뮬레이션 결과 기존의 논문보다 간단해진 회로 구성으로 더욱 높은 주파수에서 동작하였다. 그리고 settling 시간도 기존의 논문의 l00ns 이상에서 5ns로 줄어듦을 확인할 수 있었다. 본 논문은 3.3V의 공급 전압에서 $0.35{\mu}m$ CMOS공정을 이용하여 설계하였고 동작 주파수는 500MHz-2GHz였고, settling 시간은 10n이하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.13-21
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• 2010

A energy efficient $V_{pp}$ generator using a variable pumping frequency for mobile DRAM is presented in this paper. The proposed $V_{pp}$ generator exploits 3 stages of a cross-coupled charge pump for energy efficiency. Instead of using a fixed pumping frequency in the conventional $V_{pp}$ generator, our proposed $V_{pp}$ generator adopts a voltage-controlled oscillator and uses variable frequencies to reduce the ramp-up time. As a result, our $V_{pp}$ generator generates 3.0 V output voltage with 24.0-${\mu}s$ ramp-up time at 2 mA current load and 1 nF capacitor load with 1.2 V supply voltage. Experimental results show that the proposed $V_{pp}$ generator consumes around 26% less energy (1573 nJ $\rightarrow$ 1162 nJ) and reduces 29% less ramp-up time (33.7-${\mu}s$ $\rightarrow$ 24.0-${\mu}s$) compared to the conventional approach.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.80-85
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has 1.04[pF] resolution and can be used as a touch key.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.