• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.59-62
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• 2010

디지털 기술의 발달로 인해 세계 각국에서 지상파 DTV 방송망을 핵심인프라로 활용하기 위한 노력이 지속되고 있다. 하지만 국내 지상파 DTV 표준인 ATSC방식은 주파수 이용관점에서 효율적이지 못한 단점을 가지고 있다. 이러한 단점을 해결하기 위해 그 동안 동일채널 중계기술이 많이 연구되어 왔다. 그러나 동일채널간섭으로 인한 신호품질 저하, 긴 처리시간, 송출전력 제한 등의 제약조건으로 인해 실제 방송망에서는 동일채널 중계기술이 활용되지 못하고 있는 실정이다. 이에 본 논문에서는 DAB용 간섭제거 기반 동일채널 중계기를 ATSC 시스템에 적용하였다. 제안하는 동일채널 중계기는 타이밍 옵셋 보상을 위한 위상 전 왜곡기법, 파일럿 성분 추정 및 제거를 위한 직류 제거기, 송/수신신호 간의 상관도를 기반으로 궤환신호의 지연시간을 추정하는 기법이 적용되었으며, 전산 모의실험을 통해 그 성능을 확인하였다. 전산 모의실험을 통해 주 송신신호보다 간섭신호가 큰 환경에서 제안한 동일채널 중계기의 간섭제거 능력을 확인하였고, 이에 따라 동일채널 중계기의 송출능력을 개선하는 동시에 짧은 처리 지연시간 및 양호한 신호품질을 얻을 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.49-56
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• 2006

This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.

• Journal of the Korean Society for Railway
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• v.20 no.4
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• pp.448-457
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• 2017

In this paper, for high speed railway propulsion systems, a single phase PWM Converter using discontinuous PWM (DPWM) was investigated. The conventional PWM Converter uses a low frequency modulation index of less than 10 to reduce switching losses due to high power characteristics, which results in low control frequency bandwidth and requires an additional compensation method. To solve these problems, the DPWM method, which is commonly used in three phase PWM Inverters, was adopted to a single phase PWM Converter. The proposed method was easily implemented using offset voltage techniques. Method can improve the control performance by doubling the frequency modulation index for the same switching loss, and can also bring the same dynamic characteristics among switches. Proposed DPWM method was verified by simulation of 100 kW PWM converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.64-72
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• 2012

Synchronization including timing recovery, frequency offset compensation, and frame synchronization is most important signal processing block in all wireless/wired communication systems. In most communication systems, synchronization schemes based on training sequences or preambles are used. WLAN standards of 802.11a/g/n released by IEEE are based on OFDM systems. OFDM systems are known to be much more sensitive to frequency and timing synchronization errors than single carrier systems. A loss of orthogonality between the multiplexed subcarriers can result in severe performance degradations. The starting position of the frame and the beginning of the symbol and training symbol can be estimated using correlation methods. Correlation processing functionality is usually complex because of large number of multipliers in implementation especially when the reference signal is non-binary. In this paper, a simple correlation based synchronization scheme is proposed for IEEE 802.11a/g/n systems. Existing property of a periodicity in the training symbols are exploited. Simulation and implementation results show that the proposed method has much smaller complexity without any performance degradation than the existing schemes.