• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.31-35
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• 2002

본 논문에서는 DVB-T 표준안의 모든 동작모드를 지원하며 임펄스 잡음 제거, 안테나 diversity 수신, 향상된 채널추정방법을 적용한 유럽향 디지털 TV 수신용 채널 칩셋의 설계에 관한 내용이다. 설계된 칩은 여러 개의 구성 블럭으로 구성되어있는데 여기에는 여러 가지의 향상된 알고리즘과 설계 아키텍쳐가 사용되었다. 가정용 가전기기들이 발생시키는 일정주기의 임펄스 잡음을 제거하기 위하여 임펄스 잡음 제거 블록을 AGC뒤에 사용하였다. 동기부는 대략적 주파수동기, 미세 주파수동기, 대략적 타이밍동기, 미세 타이밍 동기 등으로 이루어져 있으며 본 설계의 주파수 보상 영역은 $\pm$280Khz, 타이밍 보상 영역은 $\pm$500ppm이다. 파일럿 신호를 이용하여 채널추정과 보상을 수행하며 기존의 선형 보간기법과 함께 4개의 파일럿 신호를 이용한 보간기법을 사용하여 이동수신환경에 대응할 수 있도록 하였다. 이와 함에 수신성능을 개선할 수 있다고 알려진 안테나 diversity 기능을 채용하여 고정 및 이동 수신시의 수신성능을 향상시켰다. 안테나 diversity를 위해서 2개 이상의 수신 칩이 사용되며 이를 위해서 본 설계에서는 MRC(Maximum Ratio Combining)알고리즘을 사용하였다 본 설계는 5층 메탈 0.18um 공정을 사용하였으며 2.7Mbit 의 메모리 소자를 포함하여 대략 300 만 게이트의 회로크기를 갖으며 100 핀 PQFP로 제작되었다. 본 논문에서는 설계된 회로의 각 블록별 기능에 대한 설명과 함께 시뮬레이션 결과와 ASIC설계결과를 기술하였다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.5 no.4
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• pp.18-29
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• 1994

In this paper, the performance of stepped serial search scheme and matched filter scheme for code acqusition in FH / CDMA are evaluated under land mobile radio communication channel environments. And delay lock loop scheme is used as code tracking system. As the results for code acquisition system, it is shown that the performance of stepped searial scheme is superior to matched filter scheme, because system complexity is reduced and system performance is improved by increasing the hopping frequency not to substitute for special hardware. Also, it is shown that its performance is improved under Rayleigh/ Rician fading environments. As the results for code tracking system, it is found that mean hold time is increased due to the increase of the number of lock state and hopping frequency, M.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.3-9
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• 2015

In this paper, we propose an initial timing and frequency synchronization scheme for low probability detection (LPD) systems with cyclic code shift keying (CCSK). The performance of the LPD system with CCSK highly depend on initial timing and frequency offset. On the other hand, the operating SNR (Signal-to-Noise Ratio) of LPD systems is usually very low. Hence, to guarantee a reliable performance of the LPD system, it is crucial to develop suitable initial synchronization algorithms. In this paper, we propose an initial timing and frequency synchronization scheme suitable for CCSK based LPD system using a repeated preamble pattern.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1351-1360
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• 1999

In frequency selective channels, conventional PN code acquisition schemes are not ideal candidates. This is because they are primarily designed for the AWGN channel. In this paper, a direct-sequence spread-spectrum(DSSS) PN code acquisition system based on digital matched filtering (DMF) with automatic threshold control(ATC) algorithm is presented and analyzed with regards to probability of detection and probability of false alarm. These two important probabilities, the probability of detection ($P_D$) and the probability of false alarm ($P_{FA}$) are derived and analyzed in considering Doppler shift, sampling rate, mean acquisition time, and PN chip rate in frequency selective Rayleigh fading channel when using serial-search method as detection technique. From computer simulation results of a DMF acquisition system model, it is shown that the performance of the acquisition system using ATC algorithm is better than that of constant threshold system.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.369-372
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• 2000

본 논문에서는 P-HEMT Gate-바이어스 튜닝에 의한 위상동기 마이크로파 발진기를 설계하였다. 설계된 유전체 발진기는 병렬궤환공진 형태로서 P-HEMT의 게이트단에서 전압을 제어하여 전압제어발진기 형태로 주파수를 가변시키므로서 안정된 위상동기신호를 나타나도록 하였다. 위상동기방식은 외부에서 제공되는 125㎒의 기준주파수를 SRD로 체배시켜 하모닉 신호를 이용한 마이크로파 샘플링 위상검파 방식으로 설계하였으며, 유전체 발진기의 자유발진신호와 샘플링 신호사이의 위상비교에 의하여 ±1㎒ 범위의 고안정 특성을 갖는 13.25㎓대역의 위상고정 발진기의 동기화와 저 위상잡음을 나타내었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.32-37
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• 2008

Satellite communication systems including the DVB-S2 (Digital Video Broadcasting - Satellite Version 2) system require operations under low signal-to-noise ratio (SNR) and large frequency offset values, and the initial frame synchronization process necessitates a robust correlation method. While a variety of conventional correlation structures exist for the initial synchronization, each method has different characteristics and performance in different channel environments. In this paper, we propose new correlation methods which exhibit enhanced performance in low SNR and large frequency offsets, and analyze their performance. The proposed methods use the magnitude sum and vector sum of extended differential correlation values, to maximize the correlation between the received signal and the synchronization sequence by using the spanned differential correlation result. The magnitude sum correlation method has better performance compared to conventional methods including the approximated ML (Maximum likelihood) method for SNR values below 4 dB with or without frequency offsets. The vector sum correlation method has improved performance over the magnitude sum method for channels with relatively small frequency offsets.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1353-1359
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• 2001

본 논문에서는 위상획득과정과 동기과정에서 trade-off 현상을 향상시킨 듀얼 위상 주파수 검출기를 제안하여 차지펌프 PLL을 설계하였다. 듀얼 위상 주파수 검출기는 상승에지에서 동작하는 POSITIVE 위상 주파수 검출기와 하강에지에서 동작하는 NEGATIVE 위상 주파수 검출기로 구성되어 있다. 제안한 차지펌프는 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, reference spurs와 전압제어발진기의 변동을 감소시킬 수 있도록 구현하였다. 제안한 차지펌프 PLL은 0.25$\mu\textrm{m}$ CMOS 공정을 사용하여 SPICE로 시뮬레이션 하였으며, 그 결과 1.6~1.85GHz의 넓은 동기범위를 나타내었다.