• Title/Summary/Keyword: 주파수 동기

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Unsteady Aerodynamic Characteristics of an Non-Synchronous Heaving and Pitching Airfoil Part 1 : Frequency Ratio (비동기 히브 및 피치 운동에 따른 에어포일 비정상 공력 특성 Part 1 : 진동 주파수 비)

  • Seunghwan Ji;Cheoulheui Han
    • Journal of Aerospace System Engineering
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    • v.17 no.6
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    • pp.54-62
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    • 2023
  • Flapping-wing air vehicles, well known for their free vertical take-off and excellent flight capability, are currently under intensive development and research. While most of the studies have explored the effect of various parameters of synchronized motions on the unsteady aerodynamics of flapping wings, limited attention has been given to the effect of nonsynchronous motions on the unsteady aerodynamic characteristics of flapping wings. In the present study, we conducted a numerical analysis to investigate the unsteady aerodynamic characteristics of an airfoil flapping with different frequency ratios between pitch and heave oscillations. We identified the motions and angle of attacks due to nonsynchronous motions. It was found that the synchronous motion produced thrust with zero lift, but the nonsynchronous motion generated a large lift with little drag. The aerodynamic characteristics of the airfoil undergoing the non-synchronous motion were also analyzed using the vorticity distributions and the pressure coefficient around and on the airfoil. When r was equal to 0.5, larger leading and trailing edge vortices were observed compared to the case when r was equal to 1.0, and these vortices significantly affected the aerodynamic characteristics of the airfoil undergoing the nonsynchronous motion. In future, the effect of pitch amplitude on the unsteady aerodynamic characteristics of the airfoil will be studied.

Efficient Clock Synchronization Schemes for Enhancing Error Performance of OFDM Wireless Multimedia Communication Systems (OFDM 무선 멀티미디어 통신 시스템의 오율성능 향상을 위한 효율적인 샘플링 클럭 동기방식)

  • 김동옥;윤종호
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.69-74
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    • 2003
  • In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

Performance Analysis of Wireless Communications between Tag and Reader in EPCglobal Gen-2 RFID System (EPCglobal Gen-2 RFID 시스템 태그와 리더간의 무선 전송 방식 성능 분석)

  • Yoon, Hee-Seok;Mohaisen, Manar;Chang, Kyung-Hi;Bae, Ji-Hoon;Choi, Gil-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.9
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    • pp.1047-1056
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    • 2007
  • In this paper, we analyze the performance of the encoding and the modulation processes in the downlink and uplink of the EPCglobal Gen-2 system through the analysis and simulation. Furthermore, the synchronization issues on time and frequency domain and the preamble architecture are evaluated. By incorporating the encoding and the modulation technigue in the downlink and uplink, we assess the performance of the EPCglobal Gen-2 system. We also introduce the encoding and backscatter modulation process as well as the BER performance of FM0 code. In addition, the importance and the role of the frequency and time synchronization, such as the preamble and frame synchronization are explained. Through the simulation in the uplink on the detection probability through preamble, we find that the detection probability approaches 1 for 13 dB $E_b/N_0$.

Performance Analysis of a Synchronization Algorithm For in Multimedia Wireless Channel (멀티미디어 무선채널 환경에서 동기 알고리즘 성능분석)

  • 김동욱;윤종호
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.880-883
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    • 2002
  • In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

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Design of Low-power Clock Generator Synchronized with the AC Power Source Using the ADCL Buffer for Adiabatic Logics (ADCL 버퍼를 이용한 단열 논리회로용 AC 전원과 동기화된 저전력 클럭 발생기 설계)

  • Cho, Seung-Il;Kim, Seong-Kweon;Harada, Tomochika;Yokoyama, Michio
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.6
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    • pp.1301-1308
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    • 2012
  • In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

PAPR Reduction Scheme Using Selective Mapping in GFDM (선택사상기법을 이용한 GFDM의 최대전력 대 평균전력 비 감소기법)

  • Oh, Hyunmyung;Yang, Hyun Jong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.6
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    • pp.698-706
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    • 2016
  • Orthogonal frequency division multiplexing (OFDM) has high peak to power ratio (PAPR). High PAPR makes problems such as signal distortion and circuit cost increasing. To solve the problemsm several PAPR reduction methods have been proposed. However, synchronization and orthogonality in OFDM systems may be a limitation to reduce latency for 5G networks. Generalized frequency division multiplexing (GFDM) is one of the possible solutions for asynchronous and non-orthogonal systems, which are more preferable to reduce the latency. However, multiple subsymbols in GFDM result in more superposition in time domain, GFDM has higher PAPR. Selective mapping (SLM) is one of PAPR reduction techniques in OFDM, which uses phase shift. The PAPR of GFDM SLM is compared to conventional GFDM and OFDM SLM in terms of PAPR reduction enhancement via numerical simulations. In addition, the out-of-band performance is analyzed in the aspect of asynchronous condition interference.

The Design of Reconstruction Filter for the Order Tracking of the Rotating Machinery (회전기기 진동의 Order Tracking을 위한 재합성 필터의 설계)

  • 정승호;박영필;이상조
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 1991.04a
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    • pp.95-98
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    • 1991
  • 회전 기기의 이상으로 인하여 발생하는 진동은 축 회전속도의 고주파 성분 (super-harmonic)이나 또는 분수조파 성분(sub-harmonic)으로 나타나는 경 우가 대부분이기 때문에 회전기기의 진동을 주파수 영역에서 해석함에 있어 파워 스펙트럼의 주파수 축을 Hz로 나타내기보다는 축 회전속도의 order로 써 나타내는 것이 매우 유용하다. 스펙트럼을 order로써 나타내기 위해서는 샘플링 시간을 축 회전속도와 동기(synchronization)시켜야 하는데 이 방법으 로는 회전축에 엔코더(encorder)를 부착하여 엔코더에서 발생하는 펄스 신호 를 이용하여 샘플링하는 방법과 order tracking 필터를 이용하는 방법이 있 다. 그러나 전자의 방법은 원하는 회전축마다 엔코더를 부착하여야 하며 경 우에 따라서는 엔코더를 부착하기가 어려운 경우도 있으며, 회전기기의 운전 개시나 종료시처럼 회전속도가 급격히 변화하는 경우에는 낮은 주파수에서 중첩(aliasig)에 의한 오차가 수반될 수도 있다. 후자의 방법은 order tracking 필터 이외에도 여러 부수장비가 필요하며 기준 주파수(즉 회전속 도)가 급격히 변화하는 경우 PLL(phase locked loop)에서 tracking 오차가 발생된다. 최근에 발표된 논문에서 일정한 시간간격으로 샘플링한 데이터들 로부터 신호를 재합성하여 회전축의 속도와 동기가 되도록 재 샘플링함으로 서 스펙트럼의 주파수를 회전속도의 order로써 나타내는 방법을 제시하였다. 그러나 위 논문에서는 신호의 재합성에 필요한 재합성 필터(reconstruction filter)의 설계 방법에 대하여 구체적인 언급이 없이 다만 결과만을 논하였다. 따라서 본 논문에서는 재합성 필터의 설계 방법에 대하여 구체적인 방법을 제시하고 또한 동기화 샘플링의 장점 및 고려 사항에 대하여 고찰하였다. 고려한 능동 소음제어 에 대해 연구하였다. 경량화 추세에 따라 지반이나 케이싱이 경량이거나 유연하여 회전축과 동적으로 연성된 경우 회전축-베어링-지반으로 이루어진 2중구조의 회전축 계 동특성을 해석할 수 있는 프로그램을 개발하므로서 회전 기계류의 진동 전반에 걸친 문제점에 대한 그 원인과 현상을 명확히 분석하여 국내의 전기 계류의 보다 신뢰성있는 설계 및 제작자료를 확보하는데 기여할 수 있게 하 였다.존의 small molecular Gd-chelate에 비해 매우 큼을 알 수 있었다. MnPC는 간세포에 흡수된 후 담도계로 배출되는 간특이성 조영제임을 확인하였다. 장비 내에서 반복 시행한 평균값의 차이는 대체적으로 유의한 차이가 없었으나, 다른 장비에서 반복 시행한 장비간의 사이에는 유의한 차이가 있는 경우가 더 많았다. 따라서 , MRS 검사를 소뇌나 뇌교의 어떤 절환에 적용하기 전에 각 장비 마다 정상 기준치를 반드시 얻은 후에 이상여부를 판 정하는 것이 필수적이라고 생각된다.EX> 이상이 적절한 진단기준으로 생각되었다. $0.4{\;}\textrm{cm}^3$ 이상의 좌우 부피차를 보이는 모든 증례에서 육안적으로도 해마위축이 뚜렷이 나타났다. 결론 : MR영상을 이용한 해마의 부피측정은 해마경화증 환자의 진단에 있어 육안적인 MR 진단이 어려운 제한된 경우에만 실제적 도움을 줄 수 있는 보조적인 방법으로 생각된다.ofile whereas relaxivity at high field is not affected by τS. On the other hand, the change in τV does not affect low field profile but strongly in fluences on both inflection fie이 and the maximum relaxivity value. The re

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A Novel Globally Asynchronous, Locally Dynamic System Bus Architecture Based on Multitasking Bus (다중처리가 가능한 새로운 Globally Asynchronous, Locally Dynamic System 버스 구조)

  • Choi, Chang-Won;Shin, Hyeon-Chul;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.71-81
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    • 2008
  • In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

Design of Carrier Recovery Circuit for High-Order QAM - Part I : Design and Analysis of Phase Detector with Large Frequency Acquisition Range (High-Order QAM에 적합한 반송파 동기회로 설계 - I부. 넓은 주파수 포착범위를 가지는 위상검출기 설계 및 분석)

  • Kim, Ki-Yun;Cho, Byung-Hak;Choi, Hyung-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.4
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    • pp.11-17
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    • 2001
  • In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.

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Test Patterns for Asynchronous Multiple-Access Frequency-Hopped Spread-Spectrum Systems (비동기 다원접속 주파수도약 확산대역 시스템을 위한 테스트 패턴)

  • Lee, Jae-Hong;Stark, Wayne E.;Oh, Sang-Hyun
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.3
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    • pp.40-49
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    • 1989
  • A variable-state block interference channel model is presented which matches asynchronous multiple-access slow frequency-hopped spread-spectrum systems which suffer from bursts of interference of variable duration. For variable-state block interference channels test pattern techniques combined with interleaving are presented from which the decoder obtain side information about channel states. By examining test patterns the decoder estimates which parts of data blocks are affected by interference and regards the parts of blocks affected by interference as erasures. Since the presence of test patterns reduces the number of bits for data transmission, test patterns are not useful for variable-state block interference channels for small hit probability, It is shown that test patterns increase the capacities of variable-state block interference channels for large hit probability. It is also shown that test patterns provide a almost full side information about channel states for certain values of parameters.

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