• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1037-1040
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• 2002

In micro-stereolithography technology, fabrication conditions that include laser power, laser scan speed, laser scan pitch, and material property of photopolymer such as penetration depth and critical exposure are considered as major process variables. But the existing scan path generation methods based only on CAD model have not taken them into account, which has resulted in cross-section dimension of low accuracy. Thus, to enhance cross-section dimensional accuracy, the physical resin solidification n phenomena should be reflected in laser scan path generation and stage operating code. In this paper, multi-line experiments based on single line solidification model are performed. And the method for improving cross-section dimensional accuracy is presented, which is to apply the database based on experimental results to laser scan path generation.

• Proceedings of the KSME Conference
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• 2005.11a
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• pp.213.1-213.1
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• 2005

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.409-410
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• 2006

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.541-542
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• 2007

• Journal of the Korean Society for Precision Engineering
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• v.25 no.7
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• pp.19-26
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• 2008

• Journal of the Korean Society for Precision Engineering
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• v.22 no.12 s.177
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• pp.205-210
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• 2005

This paper addresses the correlation between the change of file size and the scanning path build time by the slicing height of STL file. Though the study about STL file has been achieved quite actively scanning path build time using STL file is not investigated so much to be satisfied. The file size depends on the number of polygon created by the slicing height specified. And this number of polygons increases in a regular rate. The correlation between the number of polygons and the scanning path build time is examined and verified.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.190-193
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• 2004

This paper presents studies on the creation time of scanning path using rapid prototype device. In the case of Jewellery, it needs to take time too much at the whole process of rapid prototype in accordance with heigh of the multi-layered. When increases the number of polygon by heigh of the Multi-layered, it has proper influence on the creation time of scanning path. Therefore, we can get the spending time and the number of polygon for the creation during increase the heigh of the multi-layered. These values are showed by the quantitative. We try to analyze relation between these and heigh of the multi-layered.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.114-118
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• 2004

This paper is compared the build time of scanning path as to laminate height of the SLC and STL file. The STL file improve the surface roughness according to slicing height. But it have the fault spending long time to the creation of scanning path by being lower slicing height. So we proposed the SLC file to improve this fault. Therefore this paper showed to the build time of scanning path by the increase of peace using the jewellery model.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.405-409
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• 1997

Voronoi diagrams are applied in varios field such as NC toolpath generation, VLSI design and robot path planning because of their geometric charcteristics. In this paper, Voronoi diagrams are introduced on polygon constructed by line segments only and with constant offset. Bisector curves for two arbitrary objects, which is the combination of line segment and arc, are defined as parametric fuction where the parameter is used as offset. Offset curves are applied on the generation of laser scanning path for the stereolithography and shows a good result from several examples.