• Journal of IKEEE
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• v.23 no.3
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• pp.1096-1099
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• 2019

In this paper, we propose the protocol for construction of smart factory. The proposed protocol for construction of smart factory consists of an OPC UA Server/Client, a technology of TSN realtime communication, a NTP & PTP time synchronization protocol, a FieldBus protocol and conversion module, a technology of saving data for data transmit latency and synchronization protocol. OPC UA server/client is a system integration protocol which makes interface industrial hardware device and supports standardization which allows in all around area and also in not independent from any platform. A technology of TSN realtime communication provides an high sensitive time management and control technology in a way of sharing specific time between devices in the field of high speed network. NTP & PTP time synchronization protocol supports IEEE1588 standardization. A fieldbus protocol and conversion module provide an extendable connectivity by converting industrial protocol to OPC. A technology of saving data for data transmit latency and synchronization protocol provide a resolution function for a loss and latency of data. Results from testing agencies to assess the performance of proposed protocol for construction of smart factory, response time was 0.1367ms, synchronization time was 0.404ms, quantity of concurrent access was 100ea, quantity of interacting protocol was 5ea, data saving and synchronization was 1,000 nodes. It produced the same result as the world's highest level.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.3
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• pp.415-421
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• 2021

This study analyzed the effect on the cooling performance of the channel shape of a heat sink for an insulated gate bipolar transistor (IGBT). A serpentine channel was used for this analysis, and the parameter for the analysis was the number of curves. The analysis was conducted using computational fluid dynamics with the commercial software ANSYS fluent. One curve in the channel improved the heat dissipation performance of the heat sink by up to 8% compared to a straight-channel heat sink. However, two curves in the channel could not improve the heat discharge performance further. Instead, the two curves caused a higher pressure drop, which induces parasitic loss for the pumping of coolant. The pressure drop of the two-curve channel case was 2.48-2.55 times larger than that of a one-curve channel. This higher pressure drop decreased the heat discharge efficiency of the heat sink with two curves. The discharge heat per unit pressure drop was calculated, and the result of the straight heat sink was highest among the analyzed cases. This means that the heat discharge efficiency of the straight heat sink is the highest.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.947-959
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• 1995

In this paper, we discuss an effort to develop a multi-agent architecture through which heterogeneous applications communicate and cooperate by means of plug-and play mechanism. Three componets are created in order to challenge the plug-and-play mechanism : meta-information, PnP agent module, and ICM. The meta- information is used to automatically set up a suitable configuration for a new plugged application, eliminating the need for direct addressing among heterogeneous applications. The PnPagent module is a homogeneous controller that operates on an application to ensure that its activities are coordin ated with those of the others within the community, provides a homogeneous communication envelope for all heterogeneous applications. The combination of these three components is used to meet the desire for implementing the plug-and-play mechanism. In this distributed, open architecture, one should be able to simply plug in a new application and it should work.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1254-1260
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• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.1
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• pp.61-69
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• 2013

In an evaluation process of aircraft flying qualities, a clear and concise application interface is important since an evaluation process requires numerous repeated evaluation. This flight evaluation program have implemented efficient flight evaluation user interface along with changed trim condition interface and composed of comprehensive evaluation interface have mounted all automated FQ evaluation modules that was selected to be compose of 14 items in respect of an unmanned fixed-wing aircraft. Accordingly when it is necessary to design the flight control system as well as to develop a FQ considered aircraft, this S/W can be utilized as a tool that is a useful test evaluation S/W with scalability and enable to reduce the time and the cost of verification and evaluation process.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.312-321
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• 2013

In this paper, high efficiency control method for flyback inverter with synchronous rectifier(SR) based on photovoltaic AC modules is proposed. In this control method, the operation of SR is classified according to the voltage spike across main switch SP. When the voltage spike across SP is lower than the rating voltage of SP, the operation of active clamp circuit is interrupted for reducing the switching loss of auxiliary switch. In this time, the SR is operated for soft-switching of SP. When the voltage spike across Sp is higher than the rating voltage of SP, the operation of active circuit is activated for reducing the voltage spike. The SR is operated for reducing the conduction loss of secondary output diode. Thus, a switching loss of the main switch can be reduced in low power region, and weighted-efficiency can be improved. A theoretical analysis and the design principle of the proposed method are provided. And validity is confirmed through simulation and experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2382-2392
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• 2014

In this paper, a new data frame structure for wavelength routing in optical ring access network(ORAN) is designed and the functions of each field in the frame are defined. In addition, the IP packet transmission to the network layer corresponding to the newly proposed structure of the protocol stack is newly presented. Tha data transmission protocol design techniques of ORAN was proposed. IP packet and broadcasting packet transmission within the sub-network, and the IP packet transmission to other sub-network was shown through the process illustration. In the process, the encapsulation and framing process of the wavelength information to routing has been described in detail. And each step takes place in a packet transfer process is demonstrated. A ring type optical access network protocol is not yet research field. ORAN data transfer protocol to send/receive module structure of a subscriber node and a control node of the two rings which analyzed the results are shown. The high-speed Internet solution is proposed that by using wavelength routing the packet transport protocol for ORAN is designed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.441-448
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• 2014

USN(Ubiquitous Sensor Network) application software has a characteristic that it controls a variety of sensor nodes based on the various target operating systems. Accordingly, many researches for efficient development of USN application software are being performed. In this paper, the attributes design technique to support attribute-based development of USN node software for multi-platform is proposed. In the proposed technique, the method to design attributes for modeling Platform Independent Model and Platform Specific Model is presented. When using the proposed technique, productivity of software development will be increased because node software design for multi-platform is easily performed by selecting values of attributes. Also, maintainability of software will be increased because node software is easily regenerated by changing attributes according to the changes of operating systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.39-46
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• 2005

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation