• Proceedings of the KWS Conference
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• v.43
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• pp.1-22
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• 2004

• The monthly packaging world
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• s.270
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• pp.59-65
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• 2015

• The Science & Technology
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• v.35 no.1 s.392
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• pp.75-77
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• 2002

• Journal of Welding and Joining
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• v.23 no.2
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• pp.41-46
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• 2005

• Journal of Welding and Joining
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• v.20 no.3
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• pp.24-30
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• 2002

• The monthly packaging world
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• s.216
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• pp.42-44
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• 2011

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.36-46
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• 1999

• Journal of the Microelectronics and Packaging Society
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• v.27 no.2
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• pp.53-58
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• 2020

Analysis of electric semiconductor packaging technology for electric vehicles was performed. Topic modeling using LDA technique was performed by collecting valid patents by deriving valid patents. It was classified into 20 topics, and the definition of technology was defined through extracted words for each topic. In order to analyze the trend of each topic, the trend of power semiconductor packaging technology was analyzed by deriving hot and cold topics by topic through regression analysis on frequency by year. The package structure technology according to the withstand voltage, the input/output-related control technology and the heat dissipation technology were derived as the hot topic technology, and the inductance reduction technology was derived as the cold topic technology.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.11-19
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• 2023

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.1-8
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• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.