• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.495-498
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• 1998

Mobile computers have restrictions for size, weight, and power consumption that are different from traditional workstations. Storage device must be smaller, lighter. Low power consumed storage devices are needed. At the present time, flash memory device is a reasonable candidate for such device. But flash memory has drawbacks such as bulk erase operation and slow program time. This causes of worse average write performances. This paper suggests a storage method which improves write performance.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.549-550
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• 2008

This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.17-22
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• 1999

In this paper, the results of the studies about a new proposal where the ONON(oxide-nitride-oxide-nitride) layer instead of the conventional ONO(oxide-nitride-oxide) layer is used as the IPD(inter-poly-dielectrics) layer to improve the data retention problem in the Flash EEPROM cell, have been discussed. For these studies, the stacked-gate Flash EEPROM cell with an about 10nm thick gate oxide and on ONO or ONON IPD layer have been fabricated. The measurement results have shown that the data retention characteristics of the devices with the ONO IPD layer are significantly degraded with an activation energy of 0.78 eV. which is much lower than the minimum value (1.0 eV) required for the Flash EEPROM cell. This is believed to be due to the partial or whole etching of the top oxide of the IPD layer during the cleaning process performed just prior to the dry oxidation process to grow the gate oxide of the peripheral MOSFET devices. Whereas the data retention characteristics of the devices with the ONON IPD layer have been found to be much (more than 50%) improved with an activation energy of 1.10 eV. This must be because the thin nitride layer on the top oxide layer in the ONON IPD layer protected the top oxide layer from being etched during the cleaning process.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.41-50
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• 2009

The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. Many researchers are studying the YAFFS, NAND flash file system, which is widely used in the embedded device. However, the existing YAFFS has two problems. First, it takes long time to mount the YAFFS file system because it scans whole spare areas in all pages. Second, the cleaning policy of the YAFFS does not consider the wear-leveling so that it cannot guarantee the duration of data completely. In order to solve these problems, this paper proposes a new content-based YAFFS that consists of a mounting time reduction technique and a content-cleaning policy by using content-based block management. The proposed method only scans partial spare areas of some special pages and provides the block swapping which enables the wear-leveling of data blocks. We performed experiments to compare the performance of the proposed method with those of the JFFS2 system and YAFFS system. Experimental results show that the proposed method reduces the average mounting time by 82.2% comparing with JFFS2 and 42.9% comparing with YAFFS. Besides, it increases the life time of the flash memory by 35% comparing with the existing YAFFS whereas no overheat is added.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of Conservation Science
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• v.25 no.4
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• pp.363-371
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• 2009

This study is purposed to investigate that current rubbing technique could be replaced by the photographic rubbing techniques with the photographic lighting and digital techniques. The lighting technique is based on the "texture description theory" using the electric flash and the intaglio epitaph was emphasized from the observation of the both side because it is purposed to decipher epitaph. The photographs were retouched using the photoshop to emphasize epitaph and the spots from the lichen on the tombstone were softened. Especially, it shows that faint epitaph could be deciphered if the digital techniques could be used practically even though some part of the epitaph was destroyed or peeled. Furthermore, it will help to investigate, protect and restore the cultural properties because it surely makes the recording of the material, weathering, peeling of the tombstone much easier than the current rubbing technique.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.82-86
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• 2019

The reliability of 3D NAND flash memory cell is affected by the charge migration which can be divided into the vertical migration and the lateral migration. To clarify the difference of two migrations, the activation energy of the charge loss is extracted and compared in a conventional square device pattern and a new test pattern where the perimeter of the gate is exaggerated but the area is same. The charge loss is larger in the suggested test pattern and the activation energy is extracted to be 0.058 eV while the activation energy is 0.28 eV in the square pattern.