• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.101-112
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• 2015

II~VI compound semiconductors, $Zn_xCd_{1-x}S$ thin films have been synthesized onto indium-tin-oxide(ITO) coated glass substrates using thermal evaporation technique. The composition ratio x($0{\leq}x{\leq}1$) was varied to fabricate different kinds of $Zn_xCd_{1-x}S$ thin films including CdS(x=0) and ZnS(x=1) thin films. Then, the deposited thin films were thermally annealed at $400^{\circ}C$ to enhance their crystallinity. The chemical composition and electronic structure of films were investigated by using X-ray photoelectron spectroscopy(XPS). The optical energy gaps of the samples were determined by ultra violet-visible-near infrared(UV-Vis-NIR) spectroscopy and were found to vary in the range of 2.44 to 3.98 eV when x changes from 0 to 1. Finally, we measured the THz characteristics of the $Zn_xCd_{1-x}S$ thin films using THz-TDS(time domain spectroscopy) system to identify the capability for electronic and optical devices in THz region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.7-18
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• 1999

We have designed and tuilt the quasioptical system for the dual channel receiver which is used for the simultaneous observation of the cosmic radio with 100GHz band and 150GHz band. The quasioptical system has been widely used to guide the beam for the millimeter and submillimeter waves. A Gaussian distribution of field and power transverse to their axis of propagation allow the simple and elegant theory of Gaussian quasioptics. Using the theory of Gaussian beam, we introduced the analysis of image beam which is applied for a wide range of frequency. In order to guide two beams from the Cassegrain antenna simultaneously, the quasioptical system and its components for the dual channel receiver were designed by using the image beam method. We have checked the characteristics of the quasioptical components and the system by using the heam measurement system, which is made by us. The quasioptical system has been installed in the dual channel receiver on the Cassegrain antenna. The performance of this system has been finally confimed through the successful simultaneous observation with two bands of the cosmic radio.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.144-155
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• 1998

The array weights that will maximize the SNR for any type of noise environment are determined by the function of the antenna design configuration and the directions of receiving target and interference signals. The conventional SLCs(sidelobe cancellers) using the SNR maximization perform worst from the saturation of the receiving system of main channel when the main antenna has pattern with high gain at the arrival angle of strong interference. In this paper, the new SLC is accomplished by using two independent antenna architecture. Main antenna is implemented with adaptive nulling, which is used for rejecting high-power interference primarily. Auxiliary antenna is realized with adaptive array for receiving interference signal to be suppressed completely, which has a characteristics of sufficient gain for every direction. The new SLC is implemented with above both antennas. We show that the new SLC, which consists of the adaptive nulling main antenna and the adaptive array auxiliary antenna, is useful in reducing the effect of strong interference like jammer, because the adaptive nulling at main antenna prevents its receiver and signal processor for saturation by strong interference. The proposed SLC has improved SNR over the conventional SLCs. The improved SNR at sidelobe region is typically more than 7 dB for a given test signal. Moreover, it improves the SNR of about 20 dB under strong interference at mainlobe.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.8-14
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• 2011

The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.90-95
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• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1927-1934
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• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.23-30
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• 2000

To compensate the nonlinearity of electroabsorption modulator(EAM) resulting from its near exponential transfer function, a semiconductor optical amplifier(SOA) that has a log transfer function is used. Since the transfer function of SOA is inverse to that of EAM, the intermodulation distortion(IMD) of EAM can be reduced by cascading SOA to EAM. Also, the RF gain can be increased by the optical gain of SOA. For these reasons, spurious free dynamic range(SFDR) of EAM is enhanced by connecting SOA to EAM in series and operating in gain salutation region. To improve the nonlinearity compensation of EAM, the increased gain of SOA is required and the slope of gain saturation, the ratio of gain to input SOA power, needs to be steep. However, signal spontaneous beat noise that is the dominant system noise increases in proportion to the gain such that the SFDR of EAM is reduced. The higher the gain of SOA is, the more ASE is increased. Thus the noise level of system is increased and the following SFDR of EAM is decreased. The slope of gain saturation region and ASE of have trade-off relation and the optimization is achieved at 8㏈ optical gain. 9㏈ enhancement of SFDR of EAM is obtained. This scheme is easy to embody the linear EAM and the integration with three components (DFB-LD, EAM and SOA) offers many merits, such as low insertion loss, low chirping and low polarization sensitivity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.