• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1724-1728
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• 2007

In this paper we propose a novel electrode structure for high transmittance in the Patterned Vertical Alignment (PVA) LC cell. We use the 'TechWiz LCD' for calculation of the director configuration and optical characteristics. We studied the area decreasing the transmittance through the electrode structure for wide viewing angle and proposed new electrode design to change LC director configuration in the area. We show the comparison of the calculated optical transmittance between the conventional PVA mode and the proposed PVA mode. From the results, we confirm that the optical transmittance of the proposed structure of the PVA cell becomes higher.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.265-268
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• 2004

기존의 셀형 제조시스템에 관한 연구는 부품과 기계간의 유사성(Similarity) ${\cdot}$ 분석하여 복잡하고 큰 규모로 인해 통제 및 조정이 매우 힘든 제조시스템을 최소의 물류비용을 갖는 개별 하부 제조 시스템(Manufacturing Cell). 그러나 이러한 연구는 설비의 비중이 큰 작업장에서 설비의 효율적인 활용을 목적으로 하는 방법론이기 때문에 전자제품 조립라인과 같이 설비보다 작업자의 비중이 더 큰 라인에서는 별도의 연구가 필요하다. 현실적으로 셀형 제조시스템을 도입하여 가시적인 성과를 거둔 사례는 전자제품 조립라인의 경우가 훨씬 많다. 본 연구에서는 전자제품 조립라인에서 적용할 수 있는 조립 셀의 개념을 확립하고 성공적인 조립 셀의 도입을 위한 방법론을 제시하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.880-886
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• 2009

Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.

• Electronics and Telecommunications Trends
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• v.2 no.2
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• pp.122-129
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• 1987

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.44-52
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• 1998

In this paper, we proposed a node architecture and cell routing strategies for ATM applications in WDM multihop networks. The proposed node architecture employs the optical delay loop for storing the cell which is failed in out-link contention. This optical delay loop allows the delay of one cell without the electro-optic conversion. Therefore, we can get the advantages of S&F(Store-and-Forward) routing in Deflection-based all-optical networks. To support the ATM applications efficiently. we considered the transmission priority of ATM cell so that high priority cell can be transmitted with lower loss and shorter delay than low priority one. Two kinds of routing strategies are designed for this architecture: Scheme-Ⅰand Scheme-Ⅱ. Scheme-Ⅰapplies S&F routing to high cell and Deflection routing to low cell, i.e., high cells are routed along the shortest path based on S&F routing, but low cells are deflected or lost. Schem-Ⅱ is similar to Scheme-Ⅰexcept that low cells can occupy the optical loop if it is available. This Scheme-Ⅱ increases the utilization of network resources without decreasing the throughput of high cell by reducing the low cell loss rate when traffic load is low. Simulation results show that our routing strategies have better performance than conventional ones under non-uniform traffic as well as uniform traffic.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.409-409
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• 2010

솔라셀은 차세대 대체 에너지 소스로 최근 큰 각광을 받고 있다. 솔라셀의 제조에 있어 가장 중요한 공정은 마이크로 결정질 및 비결정질 실리콘(uC-Si:H and a-Si:H) 박막을 증착하는 PECVD (Plasma Enhanced CVD)공정이다. 현재까지 이 증착공정을 위한 플라즈마 소스로 CCP(Capacitively Coupled Plasma)가 주로 사용되어 왔다. 그러나, CCP를 플라즈마 소스를 사용한 경우 솔라셀 대량 생산 적용시 다른 방법들에 비해 긴 공정 시간이 해결해야 할 문제점으로 대두되었다. 본 발표에서는 솔라셀의 대량 생산을 위한 마이크로 결정질 실리콘 박막 증착에 있어 현 시점에서 해결되어야 할 문제점에 대해 고찰해 보고자 한다. 현재까지 이러한 문제점들을 해결하기 위해 적용되어 왔던 플라즈마 소스들을 나열하고 이러한 플라즈마 소스에 대한 특성 및 문제점들을 고찰한다. 또한, PECVD 공정상의 문제점을 해결하기 위한 플라즈마 조건을 플라즈마 벌크에서의 전자에너지 분포를 기준으로 제시하고자 한다. 솔라셀용 결정질 실리콘 박막 증착용 플라즈마 소스로 hollow cathode 방전이 가장 유력시되고 있다. 본 연구에서는 CCP 플라즈마에서 hollow cathode 방전시 발생되는 플라즈마 특성에 대한 기초 연구를 제시한다. 기초 연구를 위해 다양한 불활성 가스인 아르콘, 헬륨, 크립톤 가스에 13.56 MHz의 RF 파워를 인가하고 방전되는 플라즈마 밀도 변화를 관찰하였다. 특히, 다양한 hole diameter에서 발생되는 플라즈마 밀도의 변화를 기존 평면 CCP 플라즈마의 밀도에 비교하여 분석함으로써 hole diameter에 따른 효과를 관찰하였다. 이러한 결과는 PIC 시뮬레이션을 통해 얻은 전자에너지 분포함수를 바탕으로 메커니즘을 논의하고자 한다. 마지막으로 솔라셀용 PECVD공정을 위해 고밀도 플라즈마 소스의 필요성뿐 만 아니라 대면적 소스의 구현에 대한 문제점을 고찰하였다. 대면적 공정에서 가장 중요한 핵심 연구 이슈는 공정 균일도를 높이는 것이다. CCP 플라즈마 소스에서 전극의 크기가 대면적화 됨에 따라 발생되는 전자기파 효과에 의한 불균일도에 대해 RF 전자기장 시뮬레이션을 통해 확인하고, 균일도 확보를 위한 방안에 대한 논의하고자 한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.6 s.348
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• pp.1-8
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• 2006

In the asynchrous OFCDM(Orthogonal Frequency and Code Division Multiplexing) system, a three-step cell search algorithm is performed for the initial synchronization in the following three steps: OFCDM symbol timing, i.e., Fast Fourier Transform(FFT) window timing is estimated employing guard interval (GI) correlation in the first step, then the frame timing and CSSC (Cell Specific Scrambling Code) group is detected by taking the correlation of the CPICH(Common Pilot Channel) based on the property yeilded by shifting the CSSC phase in the frequency domain. Finally, the CSSC phase within the group is identified in the third step. This paper proposes a modification code(PCSSCG:Patial Cell Specific Scrambling Code Group) of the conventional CPICH based cell search algorithm in the second step which offers MS(Mobile Station) complexity reductions with the nearly same performance. The proposed method is to be compared and verified through the computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.69-76
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• 2006

This paper proposes a self-repair system which is able to self-repair in cell unit by imitating the structure of living beings. Because the data of artificial cells move even diagonally, our system can self-repair faults not in column unit, but in cell unit. It leads to design an efficient self-repair system for multiple faults. Moreover, in artificial cell design, the usage of logic-based design method has smaller system size than that of the previous register-based design method. Our experimental result for 2-bit up/down counter shows 40.3% reduction in hardware overhead, compared to the previous method [6].