• Title/Summary/Keyword: 전자배치

Search Result 631, Processing Time 0.026 seconds

배치 알고리즘에 대한 고찰

  • Jeong, Yong-Jin;Son, Jin-Woo
    • Electronics and Telecommunications Trends
    • /
    • v.3 no.1
    • /
    • pp.99-109
    • /
    • 1988
  • 전자회로의 설계 자동화에 있어 중요한 단계인 레이아웃(layout)의 주기능은 배치(placement)와 배선(routing)이라 할 수 있으며, 그중 배치는 크게 constructive와 iterative의 두 부류로 나누어진다. 이들의 가장 주된 목적은 배치의 다음과정인 배선(routing)에서 높은 배선율(routability)을 이룰 수 있도록 하는 데 있다. 본고에서는 배치에 있어서 일반적으로 사용되는 알고리즘과 개발동향에 대해 살펴봄으로써 앞으로 새로운 알고리즘의 개발과 자동설계 시스팀의 효율적인 사용에 도움이 되도록 하였다.

A Study on Reliability-driven Device Placement Using Simulated Annealing Algorithm (시뮬레이티드 어닐링을 이용한 신뢰도 최적 소자배치 연구)

  • Kim, Joo-Nyun;Kim, Bo-Gwan
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.5
    • /
    • pp.42-49
    • /
    • 2007
  • This paper introduces a study on reliability-driven device placement using simulated annealing algorithm which can be applicable to MCM or electronic systems embedded in a spacecraft running at thermal conduction environment. Reliability of the unit's has been predicted with the devices' junction temperatures calculated from FDM solver and optimized by simulated annealing algorithm. Simulated annealing in this paper adopts swapping devices method as a perturbation. This paper describes and compares the optimization simulation results with respect to two objective functions: minimization of failure rate and minimization of average junction temperature. Annealing temperature variation simulation case and equilibrium coefficient variation simulation case are also presented at the two respective objective functions. This paper proposes a new approach for reliability optimization of MCM and electronic systems considering those simulation results.

트랜지스터의 게이트 크기를 고려한 Rule-based 배치 프로그램 개발

  • Park, Seong-Beom;Jang, Yeong-Jo;Lee, Cheol-Dong
    • ETRI Journal
    • /
    • v.9 no.1
    • /
    • pp.49-56
    • /
    • 1987
  • 본고에서는 트랜지스터의 게이트 크기, 연결관계를 표현하는 입력 회로 정보와 트랜지스터가 배치될 규격을 표시하는 78개의 rule을 이용해 효과적인 배치를 행하는 rule based 배치 프로그램에 대해 기술했다. 본 연구의 결과는 이후 진행될 배선 연구에 이용되어 트랜지스터 회로의 레이아웃 시스팀을 구축하기 위해 응용될 것이다. 프로그램은 VAX-II/750 UNIX 4.2 BSD하의 Franzlisp으로 개발되었다.

  • PDF

Efficient Global Placement Using Hierarchical Partitioning Technique and Relaxation Based Local Search (계층적 분할 기법과 완화된 국부 탐색 알고리즘을 이용한 효율적인 광역 배치)

  • Sung Young-Tae;Hur Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.42 no.12
    • /
    • pp.61-70
    • /
    • 2005
  • In this paper, we propose an efficient global placement algorithm which is an enhanced version of Hybrid Placer$^{[25]}$, a standard cell placement tool, which uses a middle-down approach. Combining techniques used in the well-known partitioner hMETIS and the RBLS(Relaxation Based Local Search) in Hybrid Placer improves the quality of global placements. Partitioning techniques of hMETIS is applied in a top-down manner and RBLS is used in each level of the top-down hierarchy to improve the global placement. The proposed new approach resolves the problem that Hybrid Placer seriously depends on initial placements and it speeds up without deteriorating the placement quality. Experimental results prove that solutions generated by the proposed method on the MCNC benchmarks are comparable to those by FengShui which is a well known placement tool. Compared to the results of the original Hybrid Placer, new method is 5 times faster on average and shows improvement on bigger circuits.

An Effecient Sensor Deployment Scheme in Wireless Sensor Networks (도로감시 센서 네트워크에서 이벤트 감지 성능 보장 카메라 센서 최적 배치 기법)

  • Choi, Yun-Bum;Kim, Yong-Ho;Kim, Hoon
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2011.04a
    • /
    • pp.1178-1180
    • /
    • 2011
  • 무선 센서 네트워크란 센서를 통해 주변환경에 대한 정보를 수집하고 센서간의 무선 통신을 이용하여 다른 센서들과 정보를 나눔으로써 하나의 네트워크를 구성하는 것이며, 최근 기술 발전으로 인해 다양한 센서들이 널리 보급되면서 다양한 응용 분야가 등장하고 있다. 최근에는 다양해져가는 센서 네트워크에서 카메라 센서 기반 도로 감시 센서 네트워크에 대한 이슈가 대두되고 있으며, 도로 감시 센서 네트워크의 영역이 점점 대규모화가 되면서 최소의 네트워크 구축 비용으로 센서 네트워크의 요구사항을 만족하는 센서 배치 문제에 관심이 증가되고 있다. 본 고에서는 카메라 센서 기반 도로 상황을 감지하는 네트워크에서 최소의 네트워크 구축비용으로 이벤트 감지에 대한 성능을 보장하는 센서 배치 기법을 고려한다. 이를 위해 카메라 센서의 이벤트 전달 및 감지 성능을 만족하는 센서간의 간격을 도출하여서 이를 센서 배치에 적용한다.

Effective Global Placement Technique Using Quadratic Programming (Quadratic Programming을 이용한 효과적인 광역배치 기법)

  • Kim Dong-Hyun;Hur Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.6 s.348
    • /
    • pp.23-29
    • /
    • 2006
  • In this paper, we propose an effective global placement technique using quadratic programming(QP). In order to resolve cell congestion problem which is a drawback of QP based placement techniques, additional force and grid pre-warping technique are used. We devised a new density function for evaluating proper additional force which depends on density. Grid pre-warping technique relocates cells over entire area according to the relative ordering between coordinates of cells. Using the additional force obtained by the new density function and applying the pre-warping technique iteratively we obtained a well-distributed global placement. Mongrel which is a middle-down methodology based placer takes such a good global placement as an initial placement and produces a final detailed placement. Experimental results show that proposed technique outperforms the FM algorithm based global placement and are comparable with the well-known leading placers, FengShui, Dragon.

Analytical Method for Aperiodic EBG Island in Power Distribution Network of High-Speed Packages and PCBs (비주기 전자기 밴드갭이 국소 배치된 고속 패키지/PCB 전원분배망 해석 방안)

  • Myunghoi Kim
    • Journal of Advanced Navigation Technology
    • /
    • v.28 no.1
    • /
    • pp.129-135
    • /
    • 2024
  • In this paper, an analytical approach for the design and analysis of an aperiodic electromagnetic bandgap (EBG)-based power distribution network (PDN) in high-speed integrated-circuit (IC) packages and printed circuit boards (PCBs) is proposed. Aperiodic EBG is an effective method to solve the noise problem of high-speed IC packages and PCBs. However, its analysis becomes challenging due to increased computation time. To overcome the problem, the proposed analytical method entails deriving impedance parameters for EBG island and the overall PDN, which includes locally placed EBG structures. To validate the proposed method, a test vehicle is fabricated, demonstrating good agreement with the measurements. Significantly, the proposed analytical method reduces computation time by 99.7 %compared to the full-wave simulation method.

Efficient Label Placement using Overlap-free Region and Background Analysis (중첩 자유 영역과 배경 분석을 이용한 효율적인 라벨 배치)

  • Lee, San-Won;Jeong, Seung-Do;Choi, Byung-Uk
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.43 no.6 s.312
    • /
    • pp.85-96
    • /
    • 2006
  • This paper deal with a method for efficient placing 2 dimensional virtual labels on the view plane. The proposed method has suitable computational costs for realtime processing and it overcomes the local minima problem which is not solved in previous automatic label placement algorithms, and also it enhances readability by placing labels in less congestion area on the view plane. Background analysis must be considered for label placement. However previous works do not concern with this problem seriously. And furthermore, automatic label placement algorithm and background analysis algorithm have been studied separately in their own field. This paper proposed the background analysis method using background color and texture component to enhance readability, and it is the first research about analyzing the background of color image and applying it in automatic label placement field. This paper shown improved placement performance through combining automatic label placement algorithm and background analysis algorithm organically, and various experiments verified it.

A New Placement Algorithm for Gate Array (새로운 게이트 어레이 배치 알고리듬)

  • Kang, Kyung-Ik;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.26 no.5
    • /
    • pp.117-126
    • /
    • 1989
  • In this paper, a new placement algorithm for gate array lay out design is proposed. The proposed algorithm can treat the variable-sized macrocells and by considering the I/Q pad locations, the routing between I/Q pads and the internal region of a chip can be automated effectively. The algorithm is composed of 3 parts. which are initial partitioning, initial placement and placement improvement. In the initial placement phase, a given circuit is partitioned into 5 sub-circuits, by clustering method with considers connectivities of cells not only with I/Q pads but also with related partitioned groups is used repeatedly to assign a unique position to each cell. In the placement improvement phase, the concept of probabilistic wiring density is introduced, and cell moving algorithm is proposed to make the density in a chip even.

  • PDF

Macro Block Placement Using Simulated Annealing (시뮬레이티드 어닐링을 이용한 마크로 블럭의 배치)

  • Park, In-Cheol;Kyung, Chong-Min
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.26 no.2
    • /
    • pp.147-154
    • /
    • 1989
  • An effective placement of macro blocks having arbitrary width and height is very important in reducing the chip area and the signal delay. In this paper, we proposed a method of macro block placement to obtain the globally optimal placement using simulated annealing, and an efficient algorithm for eliminating the overlaps between the rectangular macro blocks which may remain even after the simulated annealing process is terminated. Each macro block was enlarged to take into account minimal routing area, and these macro blocks were compacted as much as possible during the placement. This procedure was implemented in C language running on MV10000/UNIX computer system, and good placements were obtained by applying this procedure to two circuits which were consisted of 50 and 160 macro blocks respectively. Several parameters giving great effects to final placements were investigated.

  • PDF