• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.2
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• pp.107-112
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• 2013

In the paper, velocity controller of switching module and temperature controller for the high-voltage static var compensator are proposed. Because of the continuous increase in demand for electric power, transmission and distribution facilities of power plant are required. There is a bottleneck problem of transportation routes according to new construction and expansion of power transmission facilities. Therefore there are researches to maximize the utilization of existing facilities and to increase transmission capacity without new construction. The previous static var compensator detects voltage of input circuit of power, switches the SCR directly and generates switching noise. The proposed method increases switching velocity and decreases noise using switching control based on the voltage between both sides of SCR. Also the proposed method enhance the stability using realtime temperature control for heating of the system from increase of switching velocity. We experiment the velocity and temperature control of the proposed high-voltage static var compensator in the real environment and verify the performance of the proposed system by applying in the real field.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.4
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• pp.8-15
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• 2000

In this paper, we realize the active PFC(Power Factor Correction) system of BF(Boost Forward) converter with PWM-PFM(Pulse Width Modulation-Pulse Frequency Modulation) control technique to control DC output voltage, to remove the noise like harmonics at output voltage, and to control the input current with sinusoidal wave synchronized by the source voltage.To achieve the desired load voltage and improved PFC, we first implement current shaping control at the inverting stage and make the converted output DC voltage with forward converter. After making the ratio of output voltage to current as 50V/1A and the duty ratio greater than 0.5. When input voltage is 30V and boost inductance is 1.1mH. we control the voltage changing rate according to the variation of load resistance using a PWM-PFM control technique. And finally we prove experimentally, we attenuated its harmonics and improved PF up to 0.96 using the current shaping technique.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1941-1948
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• 1997

In this paper, the power efficient linear upconversion mixer which is a functional circuit in transmit path of intermediate frequency(IF) part of Code Division Multiple (CDMA) cellular phone was explained. In generally, the low CMOS devices limits the implementation of upconversion mixer especially for lower loads. Using replica transconductor, the linear range is extended up to the limit. Thiscircuit was imprlemented using $0.8{\mu}\textrm{m}$ N-well CMOS technology with 2-poly/2-metal. The active area of chip is $0.53mm{\times}0.92mm$. The power consumption is 30mW with 3.3V suply voltage. The 1dB conpression characteristics is -27.3dB with $25{\Omega}$. load and being applied by 2-tone input signal. The mixer operates properly above 200MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1734-1745
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• 1996

In this paper, a modified fixed-delay tree search with decision feedback(FDTS/DF) for compensation of non-linear distortion in digital magnetic recording channels is discussed. Since the nonlinear distortion, which becomes significant as recording density increases, is generally well modeled by the discrete Volterra series, the proposed equlizer is composed of a nolinear feedforward filter, a linear feedback filter, and a nonlinear distorton table, the values of which are determined by considering the effect of nonlinear distortion due to future data as well as the previous and current one. At the decision stage of FDTS, a path minimizing the branch metric is chosen by using the previously detected values, current predicted value, and future predicted value. We compare the performance of the linear FDTS/DF, the previous nonlinear FDTS/DF, and the proposed nonlinear FDTS/DF by computer simulation, and confirm that the proposed one chieves the best performance at high-density recording.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.772-779
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• 2012

In the current MANET, DOS or DDOS attacks are increasing, but as MANET has limited bandwidth, computational resources and battery power, the existing traceback mechanisms can not be applied to it. Therefore, in case of traceback techniques being applied to MANET, the resource of each node must be used efficiently. However, in the traceback techniques applied to an existing ad hoc network, as a cluster head which represents all nodes in the cluster area manages the traceback, the overhead of the cluster head shortens each node's life. In addition, in case of multi-hop clustering, as one Cluster head manages more node than one, its problem is getting even worse. This paper proposes TNA(Traceback against Network Attacks) based on multihop clustering using the depth of tree structure in order to reduce the overhead of distributed information management.

• Korean Business Review
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• v.15
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• pp.1-24
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• 2002

Many of the universities in Korea recently is changing the school policy oriented from the supply approach to the demand as the case of business companies. Customer orientation is the key point of the customer satisfaction. But there are few studies focused on the satisfaction of students as a customer. In this paper, we studied the components of satisfaction in university life, the factors affecting on the satisfaction of students, and the relationship among them. The principal components of satisfaction in university life are services related to the activities of students, the utilization of welfare facilities, curriculum, the adminstration on students, and the department office. Factors affecting on the satisfaction of students are expectation, pride, self evaluation on learning, and special activities. Demographic variables, for example, sex, grade, colleges, and so on are also important factors. We also found the fact that the pride was the most important factor, and it gives positive drive on the satisfaction of students in university life. It gives us the important implication to the school policy.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of IKEEE
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• v.20 no.3
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• pp.260-264
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• 2016

The MAX77846, which is compatible with MAX77826, is a sub-power management IC (PMIC) for the latest Wearable Watch and 3G/4G smart phones. The MAX77846 contains N-MOSFET (N channel Metal-Oxide Semiconductor Field-Effect Transistor), a high-efficiency regulator, and comparator, etc to power up peripherals. The MAX77846 also provides power on/off control logic for complete flexibility and an $I^2C$ (Inter Integrated Circuit) serial interface to program individual regulator output voltages. In this paper, the simplified power macro-model based on MAX77846 is designed to verify the performance of the battery voltage in terms of current and time, and simulated by using of the LTspice. In addition, it is verified how much time can the charged battery capacity for Samsung Galaxy Gear 2 be used to operate a specified function after measuring the currents flowing to carry out the main functions in real time, which will be applicable to design parameters for the advanced power module