• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.262-267
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• 2006

We proposed a PPLN fabrication setup that measures the voltage and current applied to $LiNbO_3$ in real time during application of a DC electric field. Because the duration for transferring a sufficient electron charge to $LiNbO_3$ increases, we are able to control the electron charge flow transferred to $LiNbO_3$ efficiently. We divided the domain inversion process of PPLN into 5 states: Nucleation (state 1), Spread of the domain inversion region under the electrode(state 2), Accumulation of the electron charge at the insulator/$LiNbO_3$ interface(state 3), Domain inversion under the insulator layer after breakdown(state 4), and Lowering the electric field applied to $LiNbO_3$ (state 5). We have found that the Threshold Point is essential for the domain inversion and that the domain inversion process must be stopped within state 3 for the optimum PPLN. Using these results, we could fabricate a stable and reproducible PPLN efficiently.

• Journal of Convergence for Information Technology
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• v.11 no.6
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• pp.7-13
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• 2021

In this paper, the function of starting the negative voltage used in the IT equipment when it is generated and the method of controlling it using a microcontroller for the function to detect the overload and respond to it are presented. To do this, the limitations of the existing negative voltage generation circuit and the problems that occur during overload were analyzed, and a circuit that detects and controls the overload condition without a separate current sensing circuit was presented. In order to confirm the effect of the proposed method, an experiment was conducted by configuring an experimental circuit. As a result of the experiment, compared to the existing negative voltage generation circuit, which falls into a latch-up state when overloaded and enters a dangerous state, the proposed circuit detects this, stop the operation of the circuit, and informs the user of such an abnormal state to take action. have. In addition, since the starting point of the circuit is determined according to the system state, the experimental result was confirmed that the starting time was significantly shortened by about 23% compared to the time switch method.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.1-10
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• 2003

Device characteristics of the Metal-Ferroclecric-Semiconductor FET(MFSFET) are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V$_{G}$ curves generated from our MFSFET simulation exhibit the accumulation, the depletion and the inversion regions clearly. The capacitance, the subthreshold and the drain current characteristics as a function of gate bias exhibit the memory windows are 1 and 2 V, when the coercive voltages of ferroelectric are 0.5 and 1 V respectively. I$_{D}$-V$_{D}$ curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I$_{D}$-V$_{D}$ curve is 1.5, 2.7, 4.0, and 5.7 ㎃, when the gate biases are 0, 0.1, 0.2 and 0.3V respectively. As the drain current is demonstrated after time delay, PLZT(10/30/70) thin film shows excellent reliability as well as the decrease of saturation current is about 18 % after 10 years. Our simulation model is expected to be very useful in the estimation of the behaviour of MFSFET devices.T devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.142-142
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• 2012

최근 반도체 산업의 발전과 동시에 소자의 집적화에 따른 단채널 효과가 문제되고 있다. 채널 영역에 대한 게이트 영역의 제어능력이 떨어지면서 누설전류의 증가, 문턱전압의 변화가 발생하며, 이를 개선하기 위해 이중게이트 혹은 다중게이트 구조의 트랜지스터가 제안되었다. 하지만 채널길이가 수십나노미터 영역으로 줄어듦에 따라 소스/드레인과 채널간의 접합형성이 어렵고, 고온에서 열처리 과정을 거칠 경우 채널의 유효길이를 제어하기 힘들어진다. 최근에 제안된 Junctionless 트랜지스터의 경우, 소스/드레인과 채널간의 접합이 없기 때문에 접합형성 시 발생하는 공정상의 문제뿐만 아니라 누설전류영역을 개선하며, 기존의 CMOS 공정과 호환되는 이점이 있다. 한편, 집적화되는 반도체 기술에 따라, 동작 시 발생하는 스트레스가 소자의 신뢰성에 중요한 요인으로 작용하게 되며, 현재 Junctionless 트랜지스터의 신뢰성 특성에 관한 연구가 부족한 상황이다. 따라서, 본 연구에서는 Junctionless 트랜지스터의 NBTI 특성과 hot carrier effect에 의한 신뢰성 특성을 분석하였다. Junctionless 트랜지스터의 경우, 축적모드로 동작하기 때문에 스트레스에 의해 유기되는 캐리어의 에너지가 낮다. 그 결과, 반전모드로 동작하는 Junction type의 트랜지스터에 비해 스트레스에 의한 subthreshold swing 기울기의 열화와 문턱전압의 이동이 감소하였다. 또한 소스/드레인과 채널간의 접합이 없기 때문에 hot carrier effect에 의한 게이트 절연막 및 계면에서의 열화가 개선되었다.

• Journal of IKEEE
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• v.23 no.1
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• pp.224-229
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• 2019

Seat of automobile is required to support the comfort to driver and passenger during the driving. The control method of the seat position is changed from manual type to power type, which means using the motor to increase the comfort of the driver. By using the motor, several problems, such as vibration, noise, and over-current, appeared. These problems can be reduced through the control of seat motor. In this study, a control technology of four control variables, which determine profile of the input voltage applying to the seat motor, is proposed to generate the current profile having soft-start and soft-stop. The current flowing through the coil by input voltage is described by mathematical modeling of power seat. It is confirmed that optimized current profile having soft-start and soft-stop can be generated from simulation using the mathematical model.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.284-284
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• 2012

본 연구에서는 다이오드 소자의 온도 증가에 따른 C-V 특성을 분석하였다. 180 kHz 주파수 조건에서 온도는 300 K에서 450 K까지 50 K 간격으로 가변하였다. 측정 결과 reverse bias 영역에서는 커패시턴스의 온도 의존성이 없었으나, forward bias 영역에서는 온도가 증가함에 따라 동일 전압에서의 커패시턴스가 증가하였다. 이로부터 온도가 증가 할수록 소자가 반전(inversion) 상태에서 축적(accumulation) 상태로 빨리 전환함을 확인하였으며, 1/C2-V 그래프로부터 온도 증가에 따른 전위장벽(Built-in potential, Vbi) 감소를 확인하였다. 전위장벽은 0.63 V에서 0.31 V로 온도 상승에 따라 약 0.1 V씩 감소하였다. 이는 energy band diagram에서 p-type 영역과 n-type 영역의 energy band 차가 감소해 공핍층 영역의 폭이 좁아짐을 의미한다. 공핍층의 두께 감소로 다이오드 전류의 급격한 증가뿐 아니라 위에서 언급한 바와 같은 C-V 특성을 보였다. 이번 연구에서는 기존의 보편화 된 I-V 측정을 통한 다이오드 소자 분석과는 달리 온도 변화에 따른 C-V 분석을 통해 소자 내부의 전위 장벽 및 공핍층 폭 감소에 따른 소자 특성 변화를 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.434-439
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• 2002

본 연구는 파장 분할 다중화(WDM：Wavelength Division Multiplexing) 방식 전송 시스템 (Transmission System)에 사용되는 어븀 첨가 광섬유 증폭기(EDFA : Erbium-Doped Fiber Amplifier)의 이득 제어(Gain Control) 방법에 관한 것으로 어븀 첨가 광섬유에서 상호 이득 포화(Cross Gain Saturation) 현상, 이득 비동질 (Gain In-homogeneity) 특성, 그리고 어븀 이온의 밀도 반전(Population Inversion)의 변화 에 의해 출력되는 다 파장 광 신호들의 광 세기가 각기 다르게 출력되는 현상을 고출력을 내도록 구성된 어븀 첨가 광섬유 증폭기와 고속 제어기를 구성하여 위 현상들을 억제하며 이득을 제어하기 위한 레이저 다이오드(Laser Diode : LD)의 제어전압 조사하고, 얻어진 결과들을 토대로 이득 제어에 적합한 방법을 제시하고 제어기를 설계한다.