• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.2
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• pp.164-170
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• 2010

In brushless DC motor, current flow should be controlled such that only properly selected 2 out of 3 phases carry current depending on the position of rotor. In order to detect position of rotor, hole sensor, encoder, optical position-detecting sensor, and magnetic position-detecting sensor are frequently employed. These sensors not only often cause malfunction in low and high temperature but they also have disadvantage of increasing cost and size of an motor system. To reduce the cost and size and to increase the robustness of the motor system, recently researches on sensorless motor dirve are very active. This paper proposes a novel unipolar PWM switching method that can improve the control problem caused by the difficulty of detecting zero crossing point at high revolution speed by minimizing the switching noise while increasing the lifespan of the drive system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.220-223
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• 2016

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.52-57
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• 2009

This paper presents a low-noise low-dropout linear regulator that is suitable for on-chip integration with RF transceiver ICs. In the bandgap reference, a stacked diode structure is adopted for saving silicon area as well as maintaining low output noise characteristic. Theoretical analysis for supporting the approach is also described. The linear regulator is fabricated in $0.18{\mu}m$ CMOS process. It operates with an input voltage range of 2.2 V - 5 V and provide the output voltage of 1.8 V and the output current up to 90 mA. The measured line and load regulation is 0.04%/V and 0.46%, respectively. The output noise voltage is measured to be 479 nV/$^\surd{Hz}$ and 186 nV/$^\surd{Hz}$ from 100 Hz and 1 kHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.36-44
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• 2012

Electrical impedance tomography is a relatively new imaging modality in which the internal conductivity (or resistivity) distribution of a object is reconstructed based on the injected currents and measured voltages through the electrodes placed on the surface of the object. In this paper, it is assumed that the relationship between the resistivity distribution and the resistance of electrodes is linear. From this linear relation, the weighting matrix can be obtained and modified iterative Landweber method is applied to estimate the internal resistivity distribution. Additionally, to accelerate the convergence rate and improve the spatial resolution of the reconstructed image, optimal step lengths for the iterative Landweber method are computed from the objective function in the least-square sense. The numerical experiments have been performed to illustrate the superior reconstruction performance of the proposed scheme.

• Journal of IKEEE
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• v.16 no.2
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• pp.102-108
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• 2012

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.21.1-21.1
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• 2009

상변화 메모리는 비휘발성 메모리이면서 빠른 동작 속도, 낮은 동작 전압 등 다양한 장점을 지니고 있어 차세대 메모리로 주목 받고 있다. 최근 상변화 메모리의 동작 전류를 감소시키기 위해 상변화 물질 및 전극 물질에 대한 연구를 진행하고 있으며, 소자의 크기를 최소화 하기 위한 연구가 진행되고 있다. 본 연구에서는 나노 임프린트 리소그래피와 전도성 AFM을 이용하여 나노급 상변화 물질의 특성을 평가하였다. 나노급 상변화 물질을 형성하기 위해 열경화성 나노 임프린트 리소그래피를 이용하여 $Ge_2Sb_2Te_5$(GST)/Mo/SiO2 기판 위에 200nm급 홀 패턴을 형성하였다. 홀 패턴에 Cr을 증착하여 리프트 오프 한 뒤 Cr을 하드 마스크로 사용하여 GST를 식각하였다. 그 결과, Mo 하부 전극 위에200nm 지름과 100nm 높이를 가지는 GST 나노 기둥을 형성하였다. GST 나노 기둥의 전기적 특성 평가를 위해 저항 측정 장비 및 펄스 발생기와AFM을 사용하였다. AFM은 접촉 모드로 설정하였으며, Pt가 코팅된 AFM tip을 사용하여 Cr 하드 마스크와 함께 상부 전극으로 사용하였다. GST 나노 기둥을 초기화 시키기 위해 I-V sweep을 하였으며, 그 결과 $1M\Omega$에서 $10\;k\Omega$으로 저항이 변화함을 확인하였다. GST 나노 기둥은 2V, 5ns의 리셋 펄스에서 비정질로 변화하였으며, 1.3V, 150ns의 셋 펄스에서 결정질로 변화하였다. 이 동작 전압으로 5번의 스위칭 특성을 평가하였으며, 이 결과는 소자 형태의 200nm 급GST의 특성과 유사하여 나노급 상변화 물질을 테스트하는 새로운 방법으로 사용될 수 있을 것이다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.28.2-28.2
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• 2009

군사적, 산업적 용도로 널리 활용되고 있는 적외선 검출기는 InSb, HgCdTe(MCT)와 같은 물질들을 감지 소자로 사용하고 있다. 현재 가장 많이 사용되는 MCT는 적외선의 전 영역을 감지할 수 있는 장점이 있지만, 대면적 제작이 어려운 단점이 있다. 이에 비해 InSb는 안정적인 재료의 특성, 높은 전하이동도($1.2\times10^6\;cm^2/Vs$) 그리고 대면적 소자 제작의 가능성 등이 높게 평가되어 차세대 적외선 검출소자로 각광 받고 있다. InSb 적외선 수광 소자는 1970년대부터 미국을 중심으로 이온주입, MOCVD 또는 MBE와 같은 다양한 공정을 이용하여 제작되어 왔으며, 앞으로도 군수용 제품을 비롯하여 산업전반에서 더욱 각광을 받을 것으로 예상된다. 하지만 InSb는 77 K에서 0.225 eV의 상대적으로 작은 밴드갭을 갖고 있기 때문에 누설전류로 인한 성능저하가 고질적인 문제로 대두되었고, 이를 해결하기 위한 고품질 절연막 연구가 InSb 적외선 수광 소자 연구의 주요 이슈 중 하나가 되어왔다. PECVD, photo-CVD, anodic oxidation 등의 공정을 이용하여 $SiO_2$, $Si_3N_4$, 양극산화막(anodic oxide) 등 다양한 물질들에 대한 연구가 진행되었고[1,2], 산화막과 반도체 계면에서의 열확산을 억제하여 계면트랩밀도를 최소화하기 위한 연구도 활발히 이루어졌다[3]. 하지만 InSb 소자의 성능개선을 위한 최적화된 산화막에 대한 연구는 여전히 불충분한 실정이다. 본 연구에서는 n형 (100) InSb 기판 (n = 0.2 ~ $0.85\times10^{15}cm^{-3}$ @ 77 K)을 이용하여 양극산화막, $SiO_2$, $Si_3N_4$ 등을 증착하고 절연막으로서 이들의 특성을 비교 분석하였다. 양극산화막은 상온에서 1 N KOH 용액을 이용하여 양극산화법으로 증착하였으며, $SiO_2$, $Si_3N_4$는 PECVD로 $150^{\circ}C$에서 $300^{\circ}C$까지 온도를 변화시켜가며 증착하였다. SEM분석과 XPS분석으로 두께의 균일도와 절연막의 조성, 계면확산 정도를 확인하였으며, I-V와 C-V 커브측정을 통해 각 절연막의 전기적 특성을 평가하였다. 이 분석들을 통해 각각의 공정 조건에 따른 절연막의 상태를 전기적 특성과 관련지어 설명할 수 있었다.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.1
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• pp.46-53
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• 2009

A new zero-current switching LLC resonant post-regulator for multi-output power system is proposed in this paper. A conventional LLC resonant converter employs extra non-isolated DC/DC converters to obtain tight-regulated multi-slave output voltages. Therefore, it has several serious problems such as a poor efficiency and high cost of production. The proposed post-regulator features low voltage and current stress across the output rectifier diodes and power switches. Moreover, the proposed post-regulator requires only one power switch instead of the bulky and expensive non-isolated DC/DC converter. Therefore, it features a simple structure and lower cost. Especially, since the proposed post-regulator can ensure the ZCS of all power switches, it has very desirable advantages such as more improved EMI characteristics and reduced switching losses. Finally, to confirm the operation, validity, and features of the proposed circuit, experimental results from a proposed zero-current LLC resonant post-regulator are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.5
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• pp.372-378
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• 2009

With the increase in capacity of photovoltaic generation systems, studies are being actively conducted to improve system efficiency. In order to develop the high performance photovoltaic power system it is required to understand the physical characteristics of the solar cell. However, solar cell models have a non-linear form with many parameters entangled and conventional methods suggested to extract the parameters of the solar cell model require some kind of assumptions, which accompanies the calculation errors, thereby lowering the accuracy of the model. Therefore, in this paper a novel method is proposed to calculate the ideality factor and reverse saturation current of the solar cell from the I-V curve measured and announced by solar cell manufacturers, derive the ideal I-V curve, and then extract the series and shunt resistances value from the difference between the ideal and measured I-V curve. Also, validity of the proposed method is demonstrated by calculating the correlation between I-V curve based on modeling parameters and I-V curve actually measured through least squares method.