• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.273-273
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• 2010

고열부하 환경에 노출되는 핵융합로의 플라즈마 대향부품은 주로 낮은 원자번호 물질-열전도가 좋은 물질-구조체의 순으로 다층 구조를 이루고 있으며, 이들 간의 우수한 접합성은 부품의 성능을 좌우하는 핵심 요소이다. 이러한 플라즈마 대향부품의 건전성을 평가하기 위해서는 고열속의 열부하를 반복적으로 인가하는 시험이 요구되며, 이를 위해 본 연구원에서는 KoHLT-1, 2의 시험시설을 운용하고 있다. 본 시설에서는 열부하원으로서 그라파이터 히터를 사용하며, 히터는 두 개의 시험 대상부품 사이에 설치되고, 히터에 고전류를 인가하여 복사열에 의해 시험 부품에 열부하를 가하게 된다. 고열부하 환경에서 열피로 시험을 위해 히터에 인가되는 전류를 시간에 따라 일정한 패턴으로 반복적으로 ON-OFF 하게 된다. 본 논문에서는 이러한 고열부하시험을 수행함에 있어 고려해야 할 여러 가지 요소에 대해 논의하였다. 우선 인가하는 열유속(heat flux) 값은 일차적으로 시험시설의 최대 출력에 의해 좌우되며, 시험대상물의 운전조건 및 열부하 반복횟수에 의해 결정된다. 열부하 반복횟수는 주어진 열유속 값에 대해 total strain이 파단에 이르는 수준에 의해 결정된다. 열부하를 인가하는 시간은 히터에 전류를 인가했을 때 요구되는 온도로 상승하는 데 걸리는 시간과 시험대상물의 온도가 더 이상 증가하지 않는데 걸리는 시간에 의해 좌우된다. 냉각시간은 길수록 시험대상물의 온도가 냉각수의 온도에 접근하게 되나 너무 길어지면 시험시간이 급격히 증가하게 되므로, 온도 감소 곡선을 검토하여 적절한 시간을 정하게 된다. 열유속 측정은 냉각수의 온도 상승값과 유량으로부터 계산하게 되며, 정확한 측정을 위해서는 열부하를 인가하는 시간이 충분히 길어야 한다. 또한 시험대상 부품에서 열부하가 인가되는 면적을 정확히 정의해야 하며, 냉각관로에 열부하가 인가되어서는 않된다. 또한 시험대상부품을 지지하는 지지구조체를 통한 열손실을 최소화해야 정확한 열유속을 측정할 수 있다. 시험대상부품을 설치할 때 히터와의 간격 또한 결정해야 할 중요한 요소이며, 간격이 좁을수록 최대 열유속 값을 증가시킬 수 있으나, 너무 가까운 경우 히터의 열변형에 의한 접촉 및 아크 방전의 가능성이 있으며, 이 경우 히터와 시험대상부품의 손상을 가져오게 된다. 시험대상물이 국제열핵융합로(ITER)의 일차벽과 같이 베릴륨이 포함되어 있는 경우 방전에 의한 손상은 인체에 유해한 오염의 원인이 될 수 있다. 또한 순간적인 방전은 고가의 고전류전원의 고장을 유발할 수도 있다. 열부하 시험 중 시험대상물의 온도를 정확히 측정하는 것은 필수적이며, 온도 변화 곡선으로부터 시험대상물의 건전성 여부를 판단할 수 있다. 이를 위해 변화를 가장 잘 탐지 할 수 있는 위치에 온도 센서를 설치하는 것이 관건이며, 이는 사전 분석을 통해 알 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.565-568
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• 2014

This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Clean Technology
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• v.28 no.4
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• pp.309-315
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• 2022

Research was conducted to derive the optimal operation conditions and the optimal cathode for using a DSA electrode as an anode to minimize electrode consumption during the removal of nitrogen from wastewater by the electro-chemical method. Of the various electrodes tested as cathodes, brass was determined to be the optimal electrode. It had the highest NO₃-N removal rate and the lowest concentration of residual NH₃-N, a by-product when Cl is present in the solution. Investigating the effect of current density found that when the initial concentration of NO₃-N was 50 mg L^-1, the optimal current density was 15 mA cm^-2. In addition, current densities above 15 mA cm^-2 did not significantly affect the NO₃-N removal rate. The effect of electrolytes on removing NO₃-N and minimizing NH₃-N was investigated by using Na₂SO₄ and NaCl as electrolytes and varying the reaction times. When Na₂SO₄ and NaCl are mixed at a ratio of 1.0 g L^-1 to 0.5 g L^-1 and reacted for 90 min at a current density of 15 mA cm^-2 and an initial NO₃-N concentration of 50 mg L^-1, the removal rate of NO₃-N was about 48% and there was no residual NH₃-N. On the other hand, when using only 1.5 g L^-1 of NaCl as an electrolyte, the removal rate of NO₃-N was the highest at about 55% and there was no residual NH₃-N.

• 전자공학회논문지 IE
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• v.45 no.1
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• pp.31-37
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• 2008

A Wibro RF down converter of 2.3GHz band is designed and implemented in this paper. The problems that can occur in the receiver LNA(Low Noise Amplifier) to minimize additional purposes. In addition, 2.3GHz band from the 75 MHz downward to minimize the losses in the process, transform and improve efficiency, and achieve stable characteristics can be used to make high frequency characteristics of the device. Wibro repeater uses a TDMA(Time Division Multiplexing Access) method is needed because the RF switch. Production criterion specification, the input voltage from +8 V 1.2A of current consumption, 60dB gain and the noise figure of less than 2.5dB, VSWR(Voltage Standing Wave Ratio) less than 1.5, more than IMD(Inter Modulation Distortion) 60dB satisfied. Environmental conditions ($-20^{\circ}C$ to $70^{\circ}C$) to pass the test of reliability in a long time, that seemed crafted Wibro down converter be applied to the Wibro repeater.

• Journal of Advanced Navigation Technology
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• v.11 no.3
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• pp.239-251
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• 2007

This thesis is about the reduction of the power consumption in GPS embedded terminals with periodic position fix to improve the time delay of position determination. In order to improve time delay of position determination during the wireless terminal is powered on, it needs to be set such that it can be periodically recalibrated by the GPS and those recalibrated values need to be saved in the terminal's memory so that it can reduce the time delay from the request of location. By using the trace of the information that's been saved in the terminal's memory, it can be set so that it'll be easier to determine whether the wireless terminal has gone into buildings and have the capability of checking if it has gone into a specific building. Likewise, while the terminal is turned on, in order calibrate the location, it needs to continuously work the GPS engine which leads to a rapid decrease in terminal's idle time. This thesis proposes some solutions regarding these issues - reducing 20 ~ 30% of the battery consumption for GPS visible situation that can occur when the wireless terminal periodically calibrates its location to determine the in-building status, and extending the idle time of the terminal by flexibly using the suggested GPS calibration time method according to wireless terminal's mobility.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.73-77
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• 2017

Recently, fingerprint sensors have widely used for personal information security, and require quality evaluation to reduce an error of their recognition rate. Quality of fingerprint sensors is evaluated by variation of their electrical resistance introducing by contacts between a probe tip and a sensor electrode, Investigation on the materials compatability and structure optimization of probe is required to reduce deformation of sensor electrode for repeatability of quality testing. Nickel, steel(SK4), beryllium copper, and phosphor bronze were considered as probe materials, and beryllium copper was the most appropriate for materials of probe tips, considering indentation and contact resistance while being contacted probe tips on electrodes. Probes of an inspection part were manufactured with the single-unit structure for physical damage prevention and parallel processing capability. Inspection repeatability was evaluated by voltage variation of fingerprint sensors when the specific current was applied. A single-unit inspection part with beryllium copper probe tips showed excellent repeatability within ${\pm}0.003V$ of its voltage variation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.694-700
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• 2009

In this paper, we propose a RFID tag antenna with low performance degradation due to nearby dielectric materials. The proposed antenna is designed to be appropriate for ink printing fabrication. The antenna is designed to operate in UHF band of $860{\sim}960$ MHz. The antenna uses a T-matching network in the middle of the main body and two parasitic patches in vicinity for complex conjugate matching with a commercial tag chip. In addition, the two parasitic patches induce currents at different dielectric constants of nearby dielectric materials. This can minimize the performance degradation due to nearby dielectric materials. The measured results show the half power matching bandwidth from 844 MHT to 1,268 MHz. It exhibits the reading distance of about 3.5 m in free space when the tag antenna is used with the commercial reader antenna (transmitting power of 20 dBm and the reader antenna gain of 6 dBi). When the tag is attached on dielectric materials of wood and FR4, the resulting reading distances are 2.61 m and 2.51 m, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.