• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2675-2677
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• 2000

본 논문에서는 광대역 입력전압에 대응 할 수 있는 직류 변환 장치(DC-DC Converter)의 제어기의 모델링 및 제어 방법에 대해서 제안한다. 일반적으로 직류 변환 장치의 주된 목적은 입력되는 직류 전압에 대해서 출력전압을 지속적이고 안정적으로 유지해 주는 것이다. 따라서, 안정적인 출력 전압을 얻는 방법으로서 제어되지 않은 직류 변환 장치에 입력전압을 안정적으로 공급해주는 방법도 고려해 볼 수 있으나, 이릴 경우 입력전류의 변화나 입력 전압이 지속적으로 변하는 경우에 대처 하기 어렵다. 따라서, 이러한 문제점들을 해결하기 위해서 출력전압을 궤환 시키고 이 신호에 의해 직류 변환 장치를 제어하는 방법을 고려한다. 또한, 단순한 제어기를 사용할 경우 그 입력전압의 범위가 소자의 한계와 안정성으로 인하여 국한적으로 한정되므로, 이러한 문제를 해결하기 위해 다수의 컨버터를 연결하고 이것을 프로세서를 사용하여 제어하는 방법을 설계한다. 모델링된 직류 변환 장치는 불연속선형 시스템(Piecewise Linear System)으로 해석되어 질 수 있으며, 아울러 각기 다른 입력 범위에서 동작하는 컨버터들에 대해서도 모델링되어야 한다. 또한 일정 간격의 입력 범위내에서 서로 다른 컨버터들을 동작시켜 줄 수 있는 방법도 고려한다. MATLab을 이용하여 파워 컨버터의 성능을 입증하고, 아울러 실제 회로의 실험을 통하여 결과를 검증한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.327-334
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• 2010

This paper deals with a single-phase dynamic voltage restorer(DVR) with a quasi Z-source topology. The proposed system based on a single-phase quasi Z-source PWM ac-ac converter which have features such as the input voltage and output voltage are sharing ground, and input current operates in continuous current mode(CCM). For the detection of voltage sag-swell, peak voltage detection method is applied. Also, the circuit principles of the proposed system are described. During the 60% severe voltage sag and 30% voltage swell, the proposed system controls the adding or missing voltage and maintains the rated voltage of sinusoidal waveform at the terminals of the critical loads. Finally, PSIM simulation and experimental results are presented to verify the proposed concept and theoretical analysis.

• Korean Chemical Engineering Research
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• v.60 no.3
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• pp.363-370
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• 2022

In this paper, an estimation algorithm for state of charge (SOC) was applied using an equivalent circuit model (ECM) and an Extended Kalman Filter (EKF) to improve the estimation accuracy of the battery system states. In particular, an observer was designed to estimate SOC along with the aged capacity. In the case of the fresh battery, when SOC was estimated by Kalman Filter (KF), the mean absolute percentage error (MAPE) was 0.27% which was smaller than MAPE of 1.43% when the SOC was calculated by the model without the observer. In the driving mode of the vehicle, the general KF or EKF algorithm cannot be used to estimate both SOC and capacity. Considering that the battery aging does not occur in a short period of time, a strategy of periodically estimating the battery capacity during charging was proposed. In the charging mode, since the current is fixed at some intervals, a strategy for estimating the capacity along with the SOC in this situation was suggested. When the current was fixed, MAPE of SOC estimation was 0.54%, and the MAPE of capacity estimation was 2.24%. Since the current is fixed when charging, it is feasible to estimate the battery capacity and SOC simultaneously using the general EKF. This method can be used to periodically perform battery capacity correction when charging the battery. When driving, the SOC can be estimated using EKF with the corrected capacity.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.244-250
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• 2012

This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.24-27
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• 2016

In this study, a 1kW Solid Oxide Fuel Cell(SOFC) test system was developed. A SOFC is the most promising power system to provide the higher efficient(over 50%) for house application area(1~10kW). To develop the optimized test system, the temperature control module that controls the preprocess and reaction condition, the flow control module that controls of the mass of reactants, and the electric loader that tests the discharge performance condition, etc. The temperature control module was designed to provide the high control resolution(under $1^{\circ}C$ at $750^{\circ}C$ of operating temperature) using K-type thermal couple. The flow control module was designed control blower and heater precisely using the phase control method. And the electric loader is designed that provide CV, CC, CR discharge mode and minimized the operating error adopting the independent DC-DC converter on analog input and output module. The performance of the developed SOFC test system showed that the accuracy of stack voltage was 0.15% at 80V and stack current was 0.1% at 100A.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.2
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• pp.81-86
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• 2006

In this paper, a new process detection circuit is proposed. The proposed process detection circuit compares a long channel MOS transistor (L > 0.4um) to a short channel MOS transistor which uses lowest feature size of the process. The circuit generates the differential current proportional to the deviation of carrier mobilities according to the process variation. This method keep the two transistor's drain voltage same by implementing the feedback using a high gain OPAMP. This paper also shows the new design of the simple high gam self-biased rail-to-rail OPAMP using a proposed self-biased super MOS composite circuit. The gain of designed OPAMP is measured over 100dB with $0.2{\sim}1.6V$ wide range CMR in single stage. Finally, the proposed process detection circuit is applied to a differential VCO and the VCO showed that the proposed process detection circuit compensates the process corners successfully and ensures the wide rage operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2359-2368
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• 2013

In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.7
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• pp.754-759
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• 2015

Nowadays, short distance communication systems with low power energy (LPE) are developed for identification and monitoring of site identification of vessel crews and passengers (SIVCP). LPE communication modules, such as Bluetooth low energy (BLE) and Zigbee, are used for short distance communications with LPE. These modules enable 1:N communications and their popularity is growing since the modules can be mounted on movable objects, such as mobile devices and human body. When these modules are used, the important factor that affects their operation time and design are the capacity and size of battery. Therefore, they must be made as small as possible, and the battery should be selected to be slightly smaller than the module. In this study, we calculate the theoretical life of batteries used in SIVCP BLE modules using data sheet and discharge characteristic graph under the condition of a 1/250 transmission-ratio (TR). We thus calculate experimental life by measuring transmission current for the same TR, and low speed mode current for a 1/5000 TR and measure long-term experimental life using 1/25 TR for days. Through these experiments, we verify experimental methods for the prediction and extension of battery life that would enable us to select appropriate sizes of batteries based on vessel usage and passenger types. The selections of the module TR and battery size are important factors affecting the cost reduction of module design, the battery maintenance, and passenger convenience.