• Polymer(Korea)
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• v.39 no.2
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• pp.317-322
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• 2015

Salinity gradient power is a system which sustainably generates electricity for 24 hrs, if the system is constructed at a certain place where both seawater and river water are consistently pumped. Since power is critically determined by the water flux and the salt rejection, a membrane of water-semipermeable aquaporin protein in cell membranes was studied for pressure-retarded osmosis. NaCl was used as a salt, and $NaNO_3$ was used as a candidate to check the ion selectivity. The water flux of biomimetic aquaporin membranes was negligible at a concentration below 2M. Also, there is no remarkable dependence of water flux and ion selectivity on concentrations higher than 3M. Therefore, the biomimetic aquaporin membrane could not be applied into pressure-retarded osmosis; however, if a membrane could overcome the current limitations, the properties shown by natural cells could be accomplished.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.65-72
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• 2010

We propose the asymmetric 2.5Gbps/622Mbps PON(Passive Optical Network) in order to reduce the bandwith of filter at receiver with inverse RZ(Return to Zero) code coded downstream and NRZ(Non Return to Zero) upstream re-modulation. I theoretically analyze BER(Bit Error Rate) performance and the power sensitivity with the optimal threshold level by performing simulation with MATLAB according to the types of downstream data. The results have shown that the optimal threshold level at the optical receiver could be saturated at 0.33 as the optical received power increase more than -26dBm to keep $10^{-12}$ of BER to a minimum. Also the power sensitivity is more improved by about 3dB by fixing the threshold level at 0.33 than the conventional receiver. The proposed system can be a useful technology for optical access networks with asymmetric upstream and downstream data rates because the optical receiver can be used without controlling threshold levels and that does not require a light source in optical network unit (ONU) and its control circuits in the optical line termination (OLT).

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.19-23
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• 2002

This paper presents a micro fluxgate magnetic sensor in printed circuit board (PCB). In order to observe the effect of the closed magnetic path, the magnetic cores of rectangular-ring and two bars were each fabricated. Each fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ~100,000. Four outer layers as an excitation and pick-up coils have a planar solenoid and are made of copper foil. In case of the fluxgate sensor having the rectangular-ring shaped core, excellent linear response over the range of -100 $\mu$T to ＋ 100 $\mu$T is obtained with 540 V/Tsensitivity at excitation square wave of 3 $V_{p-p}$ and 360 KHz. The chip size of the fabricated sensing element is $7.3 \times 5.7\textrm{mm}^2$. The very low power consumption of ~8 mW was measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.n.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.387-396
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• 2004

A scheme to evaluate the number of users and cell coverage of a WCDMA supporting multi-rate traffic is newly presented through calculation of the realizable Erlang capacity from a derived blocking probability and the path loss from the COST231 Walfisch-Ikegami(W) model. We evaluate the voice-data Erlang capacities at various data rates of 15 kbps to 960 kbps and it is shown that they have a linear relationship to each other. When the E$\_$b//N$\_$o/ is low from 4 ㏈ to 3 ㏈ in case of voice capacity of 50 Erlang at 8 kbps, the result shows the increase for the data capacity of 10 Erlang and the enlargement of 100 m for the cell coverage at low rate of 15 kbps, and the increase of 0.11 Erlang and the enlargement of 40 m at high rate of 960 kbps. The increase of the blocking probability results in the increase of the Erlang capacity, but not an effect on the cell coverage, and the increase of active users in a cell results in the decrease of the coverage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.306-306
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• 2008

기계적 에너지를 전기적 에너지로 변환하는 에너지 변환소자인 압전 세라믹스는 액추에이터, 변압기, 초음파모터, 초음파 소자 및 각종 센서로 응용되고 있으며, 그 응용분야는 크게 증가하고 있다. 최근에는 이러한 압전 소자를 앞으로 도래하는 ubiquitous, 무선 모바일 시대의 휴대용 전자제품, robotics, MEMS 분야 등의 대체 에너지원으로 응용하기 위한 연구가 진행되고 있다. 특히 인간의 걷기 운동 등과 같은 일상적인 동작으로 필요한 전력을 얻을 수 있고, 세라믹 소자를 이용하기 때문에 전자노이즈가 발생되지 않을 뿐 아니라 반영구적으로 사용할 수 가 있어서, 기존 이차전지를 대체 또는 보완 할 수 있는 방안도 검토되고 있다. PZT계 세라믹스는 높은 유전상수와 우수한 압전특성으로 전자세라믹스 분야에서 가장 널리 사용되어지고 있지만 $1200^{\circ}C$ 이상의 높은 소결온도 때문에 $1000^{\circ}C$ 부근에서 급격히 휘발되는 PbO로 인한 환경오염과 기본조성의 변화로 인한 압전 특성의 저하가 문제시 되고 있다. 또한 적층 세라믹스의 제작 시 구조적 특성상 내부전극이 도포된 상태에서 동시 소결이 필요한데, 융점이 낮은 Ag전극 대신 값비싼 Pd나 Pt가 다량 함유된 Ag/Pd, Ag/Pt 전극이 사용되고 있어 경제성이 떨어지는 단점을 갖게 된다. 순수 Ag 전극을 사용하거나 Ag의 비율이 높은 내부전극을 사용하기 위해서는 $900^{\circ}C$ 이하에서 소결되고 우수한 전기적 특성을 보이는 압전 세라믹스를 개발 하는 것이 필요하다. 따라서 본 연구에서는 압전특성이 우수한 $(Pb_{1-x}Cd_x)(Ni_{1/3}/Nb_{2/3})_{0.25}(Zr_{0.35}/Ti_{0.4})O_3$ 계의 조성을 설계하고, 소걸온도를 낮추기 위해서 2 단계 하소법을 이용하였다. 또한 $MnCO_3$, $SiO_2$, $Pb_3O_4$ 등을 소량 첨가하여 액상 소결 특성을 부여하여 소결 온도를 감소시키려는 시도도 하였다. 분말을 볼 밀링 (ball milling)을 통해 24시간 동안 혼합하고, 혼합된 분말은 $800^{\circ}C$에서 2시간 동안 하소하였다. 하소한 분말을 다시 72시간 동안 볼 밀링 하여 최종 분말을 얻었다. 최종 분말에 PVB를 첨가하여 직경 15mm의 디스크 형태로 성형한 후, 850~$975^{\circ}C$ 범위에서 온도를 변화시키면서 소결을 하였다. 최종 분말 및 소결된 시편을 XRD분석을 통하여 상을 확인하였고, SEM을 이용하여 미세조직을 관찰 하였다. 전기적 특성을 평가하기 위하여 두께를 1mm로 연마한 시편에 Ag 전극을 도포하여 $650^{\circ}C$에서 열처리한 후, 분극처리 하였다. 압전특성은 $d_{33}$-meter로 측정하였고, impedance analyzer를 이용하여 압전 특성 (전기기계결합계수 및 기계적품질계수)을 측정 하였다. 또한 강유전체 특성 평가 장치 (Precision-LC)를 이용하여 분극-전계 특성을 평가하였다. 이상의 연구를 통하여 소결 온도가 $900^{\circ}C$인 경우에서도 양호한 압전 특성을 확보 할 수 있었다.

• The KIPS Transactions:PartD
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• v.15D no.6
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• pp.755-766
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• 2008

Recently, NAND flash memory is becoming into the spotlight as a next-generation storage device because of its small size, fast speed, low power consumption, and etc. compared to the hard disk. However, due to the distinct characteristics such as erase-before-write architecture, asymmetric operation speed and unit, disk-based systems and applications may result in severe performance degradation when directly implementing them on NAND flash memory. Especially when a B-tree is implemented on NAND flash memory, intensive overwrite operations may be caused by record inserting, deleting, and reorganizing. These may result in severe performance degradation. Although ${\mu}$-tree has been proposed in order to overcome this problem, it suffers from frequent node split and rapid increment of its height. In this paper, we propose Log-Structured B-Tree(LSB-Tree) where the corresponding log node to a leaf node is allocated for update operation and then the modified data in the log node is stored at only one write operation. LSB-tree reduces additional write operations by deferring the change of parent nodes. Also, it reduces the write operation by switching a log node to a new leaf node when inserting the data sequentially by the key order. Finally, we show that LSB-tree yields a better performance on NAND flash memory by comparing it to ${\mu}$-tree through various experiments.

• Korean Journal of Construction Engineering and Management
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• v.17 no.4
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• pp.76-86
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• 2016

Recently, the Contracts of International Construction Business has been decreased from the beginning of 2015 in Korea, although it has been steadily increased until 2014. This trend could be caused by Low-Price Contracts, the lack of Know-how and experience in operating, the poor management of Claims and Low-Profitability in Business. It has been recognized that the qualitative improvement of Business Contacts are necessary for successful Projects. In the Bidding Process, therefore, Experience data as In-House Data and Lessons Learned for projects should be strategically involved to assure riskless offers. Accordingly the Proposal Process are needed to be organized and enhanced by including processes for risks review about technical, marketing and commercial part during the bidding. This paper proposes a Risk Management Process model during Bidding Phase, using Risk Evaluation Method through the project life-cycle. The Concept of Model is to define CSF (Critical Success Factor) in the bidding process and Risk Factors are linked to CSF and Organization based on RAM (Responsibility assignment matrix).