• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.12
• /
• pp.106-115
• /
• 2003

Diverse multimedia services will be deployed at hand on 3G-and-beyond multi-service CDMA systems in order to satisfy different quality of service (QoS) according to traffic types. In order to use appropriate resources efficiently the call admission control (CAC) as a major resource control mechanism needs to be used to take care of efficient utilization of limited resources. In this paper, we propose a QoS-aware CAC (QCAC) that is enabled to provide service fairness and service differentiation in accordance with priority order and that applies the different thresholds in received power considering different QoS requirements such as different bit error rates (BER) when adopting total received power as the ceil load estimation. The proposed QCAC calculates the different thresholds of the different traffic types based on different required BER applies it for admission policy, and can get service fairness and differentiation in terms of call dropping probability as a main performance metric. The QCAC is aware of the QoS requirement per traffic type and allows admission discrimination according to traffic types in order to minimize the probability of QoS violation. Also the CAC needs to consider the resource allocation schemes such as complete sharing (CS), complete partitioning (CP), and priority sharing(PS) in order to provide fairness and service differentiation among traffic types. Among them, PS is closely related with the proposed QCAC having differently calculated threshold per each traffic type according to traffic priority orders.

• Clean Technology
• /
• v.29 no.4
• /
• pp.255-261
• /
• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.

• Proceedings of the Korean Society for Agricultural Machinery Conference
• /
• 2017.04a
• /
• pp.171-171
• /
• 2017

전산유체역학(CFD: Computational Fluid Dynamics)를 이용한 스마트팜 환경 내부의 정밀 제어 연구가 진행 중이다. 시계열 데이터의 난해한 동적 해석을 극복하기위해, 비선형 모델링 기법의 일종인 인공신경망을 이용하는 방안을 고려하였다. 선행 연구를 통하여 환경 데이터의 비선형 모델링을 위한 Tensorflow활용 방법이 하드웨어 가속 기능을 바탕으로 월등한 성능을 보임을 확인하였다. 그럼에도 오프라인 일괄(Offline batch)처리 방식의 한계가 있는 인공신경망 모델링 기법과 현장 보급이 불가능한 고성능 하드웨어 연산 장치에 대한 대안 마련이 필요하다고 판단되었다. CFD 해석을 위한 Solver로 SU2(http://su2.stanford.edu)를 이용하였다. 운영 체제 및 컴파일러는 1) Mac OS X Sierra 10.12.2 Apple LLVM version 8.0.0 (clang-800.0.38), 2) Windows 10 x64: Intel C++ Compiler version 16.0, update 2, 3) Linux (Ubuntu 16.04 x64): g++ 5.4.0, 4) Clustered Linux (Ubuntu 16.04 x32): MPICC 3.3.a2를 선정하였다. 4번째 개발환경인 병렬 시스템의 경우 하드웨어 가속는 OpenCL(https://www.khronos.org/opencl/) 엔진을 이용하고 저전력 ARM 프로세서의 일종인 옥타코어 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea) SBC(Single Board Computer)를 32식 병렬 구성하였다. 분산 컴퓨팅을 위한 환경은 Gbit 로컬 네트워크 기반 NFS(Network File System)과 MPICH(http://www.mpich.org/)로 구성하였다. 공간 분해능을 계측 주기보다 작게 분할할 경우 발생하는 미지의 바운더리 정보를 정의하기 위하여 3차원 Kriging Spatial Interpolation Method를 실험적으로 적용하였다. 한편 병렬 시스템 구성이 불가능한 1,2,3번 환경의 경우 내부적으로 이미 존재하는 멀티코어를 활용하고자 OpenMP(http://www.openmp.org/) 라이브러리를 활용하였다. 64비트 병렬 8코어로 동작하는 1,2,3번 운영환경의 경우 32비트 병렬 128코어로 동작하는 환경에 비하여 근소하게 2배 내외로 연산 속도가 빨랐다. 실시간 CFD 수행을 위한 분산 컴퓨팅 기술이 프로세서의 속도 및 운영체제의 정보 분배 능력에 따라 결정된다고 판단할 수 있었다. 이를 검증하기 위하여 4번 개발환경에서 운영체제를 64비트로 개선하여 5번째 환경을 구성하여 검증하였다. 상반되는 결과로 64비트 72코어로 동작하는 분산 컴퓨팅 환경에서 단일 프로세서 기반 멀티 코어(1,2,3번) 환경보다 보다 2.5배 내외 연산속도 향상이 있었다. ARM 프로세서용 64비트 운영체제의 완성도가 낮은 시점에서 추후 성공적인 실시간 CFD 모델링을 위한 지속적인 검토가 필요하다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.10
• /
• pp.1050-1060
• /
• 2009

In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than $4^{\circ}$ max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.

• Tunnel and Underground Space
• /
• v.22 no.3
• /
• pp.173-180
• /
• 2012

In this study, diagonal ventilation circuits that are advantageous in air flow direction control were studied. Based on the results of the study, it could be seen that air volumes in diagonal ventilation circuits could also be calculated using numerical formulas or programs if the air volumes and air flow directions to be infused into diagonal branches are determined in advance as with other serial/parallel circuits. To apply the results, design plans for high level radioactive waste repositories applied with diagonal ventilation circuits and parallel ventilation circuits. To compared the each design plans and obtain expected operation results, ventilation network simulations were conducted through the Ventsim program which is a ventilation networking program. Based on the results, in the case of diagonal repositories that was expected to cause great increases in resistance, fan pressure was 1570 pa, total flux was 84 $m^3/s$, fan efficiency was 76.4%, fan power consumption was 181.2 kW and annual fan operating costs were 178,710,838 and thus maximum around 8% differences were shown in pressure and flux values and a difference of around 1.5% was shown in terms of operating costs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.21 no.11
• /
• pp.746-752
• /
• 2020

As environmental issues have been taken seriously, the number of solar power generation facilities has rapidly increased in Korea. The voltage at the output stage of an inverter increases in a system that connects a small-capacity photovoltaic power generation to low-voltage power distribution. This degrades the quality of the low-voltage distribution system and adversely affects the load facility. In this study, a solution was obtained to increase the voltage at the output stage of the solar inverter according to the connection of the low-voltage distribution system. The voltage can be controlled by using reactive power factor control inverters. If the secondary tap is adjusted, the voltage can be adjusted to about 15 V, but there is a problem in that the tap is not adjusted unless the KEPCO distribution regulation voltage is out of the range of 220±13V. If the number of inverters is limited, the inverter can be started within the inverter overvoltage range. If it is connected to three phases, the voltage is distributed. The results indicated that power factor control and active voltage control inverters were easy to apply in the field.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.3
• /
• pp.194-201
• /
• 2014

This paper is able to be solved by improving degradation in multi-path environment by adjust beam pattern angle through modifying pulse phase of each antennas by using TRM (Transmitter Receiver Module). Beam Scanning Array Antenna, which is transmitter/receiver that improves degradation in multi-path environment without any signal distortion, is designed and manufactured. Beam Scanning Array Antenna should be able to send/receive signal at the antenna's longitudinal part without distortion and should not influences other systems. Also, it should include target detecting ability by beam steering.Dispersion characteristic of Beam Scanning Antenna, which is designed, is analysed by using fidelity, and steering and radar resolution performance is verified by using $1cm{\times}1cm$ sized target. To manufacture Beam Scanning Array Antenna, control board and GUI, which is able to control Vivaldi Antenna for IR-UWB, Tri-Band Wilkinson power divider, and TRM (Transmitter Receiver Module), is designed. Throughout this research, developed Beam Scanning UWB Array Antenna system is adoptable for radar application field. and time domain analysis techniques by using network analyser made the antenna characteristics analysis for setting up antenna more accurate. In addition, it makes beam width checking without difficulties.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.12
• /
• pp.1380-1393
• /
• 2010

This paper presents a design, fabrication and the test results of planar active electronically scanned array(AESA) radar prototype for airborne fighter applications using transmit/receive(T/R) module hybrid technology. LIG Nex1 developed a AESA radar prototype to obtain key technologies for airborne fighter's radar. The AESA radar prototype consists of a radiating array, T/R modules, a RF manifold, distributed power supplies, beam controllers, compact receivers with ADC(Analog-to-Digital Converter), a liquid-cooling unit, and an appropriate structure. The AESA antenna has a 590 mm-diameter, active-element area capable of containing 536 T/R modules. Each module is located to provide a triangle grid with $14.7\;mm{\times}19.5\;mm$ spacing among T/R modules. The array dissipates 1,554 watts, with a DC input of 2,310 watts when operated at the maximum transmit duty factor. The AESA radar prototype was tested on near-field chamber and the results become equal in expected beam pattern, providing the accurate and flexible control of antenna beam steering and beam shaping.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.11A
• /
• pp.882-890
• /
• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.2
• /
• pp.309-316
• /
• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.