• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.245-251
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• 2017

The proposed variable pawer divider in this paper is composed of one equal power 2-way Wilkinson power divider, two variable phase shifters with 90-degree phase variation to be connected two output paths of the 2-way power divider, and one branchline coupler to combine output signals of two variable phase shifter. The proposed variable power divider can theoretically have an arbitrary power division ratio ranging from ${\infty}:1$ to ${\infty}:1$ due to 90-degrees phase variation of two phase shifter. The proposed power divider circuit fabricates on laminated TLX-9(h=20 mil, er=2.5; Taconic) with a center frequency of 1.7 GHz. The power division ratio of the fabricated prototype varies from about 1:100 to 200:1, with an input reflection characteristic(S11) of below -16 dB, an insertion loss of about -1.0 dB, and an isolation characteristic of below -17 dB between two output ports in the range 1.65-1.75 GHz.

• Journal of IKEEE
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• v.24 no.3
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• pp.803-813
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• 2020

This paper presents a high efficiency resonant flyback converter using a single-chip microcontroller. The proposed converter primary performs the resonant switching by applying the asymmetrical pulse-width modulation (APWM) to the half-bridge power topology. And the converter secondary uses the diode flyback rectifier as its power topology and operates with the zero current switching (ZCS). Thus the proposed converter achieves high efficiency. The total structure of proposed converter is very simple because it uses a single-chip microcontroller and bootstrap circuit for its control and drive, respectively. First, this paper describes the converter operation according to each operation mode and shows its steady-state analysis. And the software control algorithm and drive circuits operating the proposed converter are explained. Then, the operation characteristics of proposed converter are shown through the experimental results of an implemented prototype based on each explanation.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.343-344
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• 2010

본 논문에서는 넓은 입출력 변동 범위를 가지는 LLC 공진형 직류-직류 변환기의 전류형 제어에 대해서 소개한다. 먼저, 전류형 제어의 개념과 목적을 설명하고 전류형 제어를 적용한 변환기를 소신호 해석을 이용해 전원단의 동특성을 확인한다. 그리고 동특성 해석을 바탕으로 전압 보상기 회로를 구성한 후, 변환기의 성능을 실험과 시뮬레이션을 통해 비교 및 검증한다. 마지막으로 전압형 제어를 이용한 변환기와 비교를 통해 전류형 제어의 우수성을 확인한다.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.347-348
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• 2010

본 논문에서는 기본적인 직류-직류 변환기 중 하나인 동기식 강압형 직류-직류 변화기를 디지털 제어로 구현함으로서 아날로그 제어기를 디지털 제어기로 변환 하는 과정에 관하여 설명한다. 먼저 전원단의 소신호 특성을 해석하여 제어대 출력전압의 전달함수를 찾아내고, 이것을 토대로 아날로그 제어기를 설계 하여 Simulink를 통하여 시뮬레이션을 수행하고, 설계된 아날로그 제어기를 바탕으로 Matlab을 이용한 Emulation 기법을 사용하여 디지털 제어기를 설계 한다. DSP(TMS320F28335)를 사용한 동기식 강압형 직류-직류 변환기에 설계된 디지털 제어기를 적용하여 안정도와 부하변동에 따른 응답 특성을 확인 한다.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1217-1219
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• 2003

신 발전 방식들 중 하나인 용융탄산염형 연료전지 발전시스템 개발과 관련하여, 연료전지로부터 생성된 전력을 전력계통에 안정되게 변환, 주입하기 위한 계통연계형 전력변환기를 설계하고 단위기기별 성능 시험을 수행한 결과이다. 100kW급 전력변환기의 구조 설계에 있어서는, 100kW급 용융탄산염형 연료전지 시스템의 정격 사양 및 스택의 운전 형태에 따라 새로운 시뮬레이션 결과의 검토를 통해 DC/DC 컨버터부, 정류부, 인버터부의 회로 구성을 확정하고, 각 부에 사용될 소자들을 연료전지 출력 및 운전 사양에 맞게 설계하였다.

• 전기의세계
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• v.36 no.9
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• pp.643-657
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• 1987

본고에서는 주로 DC 서어보와 AC 서어보 제어기의 실례, 각 서어보 전동기에 동력을 공급하는 전력변환기의 종류에 대하여 설명하고자하며, 마지막으로 최근 유도전동기 서어보시스템에 제어이론 도입에 의해 진전된 제어의 실현 동향을 알아보고 산업계에 적용한 사례에 관하여 알아보았다.

• Journal of the Korean Society of Radiology
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• v.6 no.6
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• pp.495-498
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• 2012

In this paper, the basic behavior of the environment and the driving time as a prediction of the lifetime of the power semiconductor devices were recorded. Radiator of a power device driving time and temperature operating environment, including cumulative record by the controller of the power converter, and doing it so you can see the power semiconductor devices for the life of the structure that the size of the change in the temperature of the semiconductor chip and the number of iterations to maintenance warranty period because of a lifetime by forecasting or replacement can be made at the appropriate time that is considered.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.