• Journal of the Computational Structural Engineering Institute of Korea
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• v.33 no.1
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• pp.55-61
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• 2020

Social infrastructure facilities that have been under construction since the country's high-growth period are undergoing rapid aging, and, thus, safety assessments of large structures such as bridge tunnels, which can be directly linked to large-scale casualties in the event of an accident, are necessary. It is difficult to construct economical and efficient wireless smart sensor networks that improve structural health monitoring (SHM) because the existing wire sensors have a short signal reach. However, low-power wide-area networks (LPWANs) are becoming popular within the Internet of Things, and enable economical and efficient SHM. In this study, the technology trends of a wireless measuring sensor based on LoRa LPWANs were investigated, and an installation and maintenance plan for this type of sensor is proposed.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
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• 2007.11a
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• pp.288-293
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• 2007

미국 911 테러 발생 이후로, 국가 기반시설(예: 송/배전 전력망, 석유/가스 파이프라인, 원자력 발전소, 정보통신 시설, 교통 시설, 금융 시설, 매스미디어 시설 등)에 대한 테러리스트의 사보타지 리스크를 관리하는 도전문제에 정부 차원이나, 기업 차원에서 국내외적으로 뜨거운 이목이 집중되고 있다. 그 가운데 에너지 시스템, 특히 원자력 발전소의 물리적 보안은 국가 안보 차원에서 매우 중대한 이슈가 되고 있다. 이는 사보타지로 인한 이러한 시스템의 파손이 국민, 작업자, 또는 외부 환경에 방사성물질 누출과 같은 중대한 결말을 초래할 수 있기 때문이다. 원전과 같은 복잡 시스템에서 설계 기준 위협이 초래할 수 있는 이러한 결말은 그 시스템의 특정 핵심 표적(예: 부품, 구역, 자산, 행위, 인원)의 방호를 통해 효과적으로 방어될 수 있다. 다시 말하면, 표적 인식에서는 어떻게 방어할 것인가에 앞서서 무엇을 방어할 것인가를 다루려는 것이다. 이 연구의 주요 목적은 여태까지 개발된 다양한 표적 인식 기법의 개발 추세를 소개하고 향후 전망을 제시하는 데에 있다. 이를 통해 표적 인식 기법의 수월성, 신뢰성, 및 경제성을 제고할 수 있으리라 본다. 표적 인식 기술의 활용성 측면에서 볼 때, 표적 인식은 하드웨어 적이거나 소프트웨어적인 방호 시스템의 설계에 필수적이므로, 신뢰성 높은 표적 인식은 다음과 같은 긍정적인 파급 효과를 줄일 수 있다: 1) 사보타지 리스크 감소에 직간접적으로 기여할 수 있다; 2) 제한적인 보안 재원을 효율적으로 할당할 수 있다; 3) 보안 대응군대의 훈련 시나리오를 개발할 수 있다; 4) 발전소 규제요건인 안전조치 계획을 비용이나 보안 측면에서 향상시켜 국민 안심(public easiness)을 도모할 수 있다. 향후에는 보다 더 광의적인 복잡 시스템 사이에서 상호 연계적인 사보타지에 대한 표적 인식의 기법들이 점검될 필요성이 있다고 본다.

• Explosives and Blasting
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• v.26 no.2
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• pp.29-37
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• 2008

In general, the size of tunnel cross section in construction site is $50{\sim}200m^2$. But, electric cable tunnel, telecommunication cable tunnel, mine tunnel. Waterproof tunnel have small cross section less than $20m^2$. There are so many problem at small sectional tunnel: restriction of equipment, dead pressure by precompression, loss of efficiency, increase of work time. Especially, explosives remainder by precompression of previous detonation is serious problem. To find its measures of dead pressure (explosives remainder), the following series of progress have been conducted: (1) survey of previous study (2) investigate causes of dead pressure (3) set up of its measures (4) application and appraisal at tunnel site. The measures, change of cut pattern, hole space over 40cm, adjustment of delay time, are proved by experimental results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.1-9
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• 2003

Many CDMA systems provide pilot channels in order to help channel estimation process. Especially in wideband CDMA systems, the number of receive diversity paths can be large due to small chip duration and high multi-path resolution capability. Hence, the received signal power of each path is small for a given total SNR (signal-to-noise ratio) and the pilot power of each path may not be sufficiently large for accurate channel estimation. When the pilot power is small, one can use decision-directed channel estimation to utilize more energy of the received data. However, the decision errors can deteriorate the quality of decision-directed channel estimation. This paper proposes a novel channel estimation method that optimally utilizes receiver decisions as well as pilot symbols with the help of estimated SER (symbol error rate) and SNR. The proposed method computes two channel estimates using the pilot and the data channel filters and optimally combines them. The simulation results show that the proposed method is robust and outperforms the conventional pilot-symbol-aided channel estimation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.40-45
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• 2009

In this paper, we introduce a mobile-type tiny sensor device that can classify the activities of daily living based on the state-dependent motion analysis using a 3-axial accelerometer in real-time. The device consists of an accelerometer, GPS module, 32bit micro-controller for sensor data processing and activity classification, and a bluetooth module for wireless data communication. The size of device is 50*47*14(mm) and lasts about 10 hours in operation-mode and 160 hours in stand-by mode. Up to now, the device can recognize three user activities ("Upright", "Running", "Walking") based on the decision tree. This tree is constructed by the pre-learning process to activities of subjects. The accuracy rate of recognizing activities is over 90% for various subjects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.27-32
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• 2008

Impulse Radio Ultra Wide Band (IR-UWB) system can be used to wireless position location system because of its unique very short pulse in the order of nanosecond. A few algorithms have been proposed to calculate location of sensors or tags. In this paper, we compare these algorithms and propose 'TDoA with wireless synchronization' as practical solution. Earlier algorithms need special logic to fix the duration to receive and send pulse or assume synchronization with wire. In proposed method, beacons synchronize each other using impulse and nodes can be made simple and cheap. We evaluated the performance and it shows 50% improved accuracy at the error range of 50cm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.271-277
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• 2004

A Si(Silicon) MEMS(Micro Electro Mechanical System) package using a doped lossy Si carrier for CPW(Coplanar Waveguide) MMICs(Microwave and Millimeter-wave Integrated Circuits) is proposed in order to reduce parasitic problems of leakage, coupling and resonance. The proposed chip-carrier scheme is verified by fabricating and measuring a GaAs CPW on the two types of carriers(conductor-back metal, doped lossy Si) in the frequency from 0.5 to 40 ㎓. The proposed MEMS package using the lightly doped lossy(15 Ω$.$cm) Si chip-carrier and the HRS(High Resistivity Silicon, 15 ㏀$.$cm) shows the optimized loss and parasitic problems-free since the doped lossy Si-carrier effectively absorbs and suppresses the resonant leakage. The Si MEMS package for CPW MMICs has an insertion loss of only - 2.0 ㏈ and a power loss of - 7.5 ㏈ at 40 ㎓.