• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.49-56
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• 2008

This paper introduces a compact analytical current conduction model of long-channel depletion-mode n-type nanowire field-effect transistors (NWFETs). The NWFET used in this work was fabricated with the bottom-up process and it has a bottom-gate structure. The model includes all current conduction mechanisms of the NWFET operating at various bias conditions. The results simulated from the newly developed NWFET model reproduce a reported experimental results within a 10% error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.1-6
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• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.339-343
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• 2005

Pt-$SrBi_2Nb_2O_9(SBN)-Pt-Y_2O_3-Si$ gate field effect transistors (MFMISFETs) have been fabricated and the SBN thin films are rapid thermal annealed in oxygen plasma. The grain size of the SBN becomes 4 times much larger than that of furnace annealed SBN films even at the same annealing temperature of $700^{\circ}C$, remnant polarization value of Pt-SBN-Pt is improved by 2 times. Using the rapid grain growth of SBN for the MFM-ISFET, memory window and programming characteristics of on/off states are fairly well improved.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.5
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• pp.1592-1596
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• 2010

According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

• Journal of the Korean Society for Railway
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• v.14 no.5
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• pp.411-415
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• 2011

DC/DC switching power converters are commonly used to generate a regulated DC output voltages with high efficiencies from different DC input sources. The voltage mode DC/DC converter utilizes MOSFET (metal-oxide semiconductor field effect transistor), inductor, and a PWM (pulse-width modulation) controller with oscillator, amplifier, and comparator, etc. to efficiently transfer energy from the input to the output at periodic intervals. The fundamental boost converter and a buck converter containing a switched-mode power supply are studied. In this paper, the electrical characteristics of DC/DC power converters are simulated by program of SPICE, and the PWM controller is implemented to check the operation. In addition, power efficiency is analyzed based on the specification of each component.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.292-294
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• 2016

이황화몰리브덴을 활용한 전계효과트랜지스터(Field Effect Transistor)는 채널 물질의 우수한 특성으로 차세대 저전력 고성능 스위치와 광전소자로 주목받고있다. Underlap 게이트 구조에서 게이트 길이(L_G), 절연체 두께(T), 절연체 상대유전율(${\varepsilon}_r$)에 따라 변화하는 소자특성을 분석하여 저전력 고성능 $MoS_2$ 전계효과트랜지스터를 위한 게이트 구조 최적화방법을 모색하였다. EDISON simulator 중 Tight-binding NEGF 기반 TMD FET 소자 성능 및 특성 해석용 S/W를 활용하여 게이트 구조에 따른 게이트 전압 - 드레인 전류 상관관계(transfer characteristic)를 얻고, Y-function method를 이용하여 채널 유효전하이동도(Effective Mobility), Sub-threshold Swing, on/off 전류비(on/off current ratio)를 추출하여 비교 분석하였다. 시뮬레이션으로 추출한 소자의 최대 채널 유효전하이동도는 $37cm^2V^{-1}s^{-1}$, on/off 전류비는 $10^4{\sim}10^5$, Sub-threshold Swing은 ~38mV/dec 수준을 보였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.271.2-271.2
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• 2013

열화학 기상 증착법은 반도체 산업에서 대면적으로 소자를 양산할 수 있는 방법 중의 하나로서, 그래핀, 이황화 몰리브덴과 같은 이차원 물질의 합성법으로 널리 이용되고 있다. 이런 이차원 물질은 층수에 따라 그 물성이 변화하므로, 층수 조절이 가능한 합성법의 필요성이 대두되고 있다. 열화학 기상 증착법으로 이차원 물질을 합성할 경우, 주요 변수로 성장 온도와 촉매 금속이 있으며 이를 적절히 조절함으로서 합성되는 그래핀의 결정성과 층수의 조절이 가능하다[1-3]. 또한, 이차원 반도체 물질로 전계효과 트랜지스터를 제작하는 경우, 얇은 두께로 인하여 표면의 환경에 민감하게 되므로 게이트 절연체가 중요한 문제로 대두되고 있으며, 이런 현상을 해결하고자 질화붕소(BN)과 같은 이차원 절연물질에 관심이 집중되고 있다. 본 연구에서는 이차원 절연체인 질화붕소의 표면 위에 그래핀을 합성하고자 하였다. 반데발스 성장법(van der Waals epitaxy growth method)으로 1. "BN/ SiO2" 2. "BN/ Ni" 3. "BN/ Cu"의 세 가지 기판을 이용하여 그래핀을 합성하였다. 합성된 그래핀의 결정성 및 층수를 확인하기 위해 라만 스펙트럼과 투과전사 현미경을 통하여 분석하였다. 또한, 이 방법으로 "그래핀/ 질화붕소/ 그래핀"과 같은 구조의 소자를 제작하여 전계효과 트랜지스터 특성을 살펴보았다.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.3 no.1
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• pp.18-25
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• 1978

The 1/f noise spectrum of short-circuited output drain current due to the Shockley-Read-Hal] recombination centers with a single lifetime in homogeneous nondegenerate MOS-field effcte transtors with n-type channel is calculated under the assumptions that the quasi-Fermi level for the carriers in each energy band can not be defined if we include the fluctuation for time varying quantities. and so 1/f noise is a majority carrier effect. Under these assumptions the derived 1/f noise in this paper show some essential features of the 1/f noise in MOS-field effect transistors. That is, it has no lowfrequency plateau and is proportionnal to the channel cross area A and to the driain bias voltage Vd and inversely proportional to the channel length L3 in MOS field effect transistors. This model can explain the discrepancy between the transition frequency of the noise spectrum from 1/f- response to 1/f2 and the frequency corresponding to the relaxation time related to the surface centers in p-n junction diodes. In this paper the results show that the functional form of noise spectrum is greatly influenced by the functional forms of the electron capture probability cn (E) and the relaxation time r (E) for scattering and the case of lattice scattering show to be responsible for the 4 noise in MOS fold effect transistors. So we canconclude that the source of 1/f noise is due to lattice scattering.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1448-1450
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• 2001

본 연구에서는 알루미늄 마스크를 이용하여 다결정 실리콘 결정립의 수평성장을 유도하는 새로운 엑시머 레이저 어닐링 방법을 제안한다. 제안된 방법은 비정질 실리콘 박막 위에 알루미늄 패턴을 형성하여 선택적으로 레이저 빔을 차단시키고, 액상 실리콘의 열을 금속박막을 통해 방출시킴으로써 다결정 실리콘 결정립의 수평성장을 유도할 수 있다. 제안된 레이저 결정화 방법을 이용하여 최대 1.6${\mu}m$의 수평성장 결정립을 형성하였고, 알루미늄 패턴의 경계로부터 결정립을 성장시킴으로써 결정립 경계의 위치를 제어하였다. 제안된 방법을 이용하여 제작한 다결정 실리콘 박막 트랜지스터는 기존의 다결정 실리콘 박막 트랜지스터에 비해 전계효과 이동도 및 온/오프 전류비 등의 전기적 특성이 우수하였다.