• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.270-277
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• 2000

A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

• 전기의세계
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• v.14 no.6
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• pp.1-7
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• 1965

This paper provides the analysis of the differential amplifier using the insulated gate, metala-oxide-semiconductor type field-effect-transistor(MOS FET), for its active element and the power drift of the amplifer. From these analytical considerations some design standardsn were found for the MOS FET differential amplifier available for the measurement of the very small current (pico-ampare range). A differential amplifier was designed and built in the view of above considerations. Its equivalent input gate voltages of the thermal drift and the power drift were 0.57mV/.deg. C in the range 25.deg. C-60.deg. C and 8.8mV/V in the range of 20% drift of its orginal value, respectively.

• Electronics and Telecommunications Trends
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• v.20 no.5 s.95
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• pp.56-69
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• 2005

유기물이 반도체 성질을 가질 수 있다는 것이 밝혀지면서 많은 여러 가지 응용분야에 많은 연구가 진행되어 왔다. 유기 반도체는 무기 반도체와 다르게 적절한 용매에 녹는다는 장점이 있다. 이 장점을 활용해 소자 제작에 직접 인쇄법인 그래픽 인쇄 방식을 사용할 수 있다. 본 기고문에서는 유기 반도체의 여러 응용 분야 중 직접 인쇄법으로 제작한 유기 전계효과 트랜지스터(OTFT)를 중심으로 기술 발전 방향과 연구 동향, 대표적 벤처 기업 등에 관하여 기술하였다.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1318-1320
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• 1998

We have investigated the electrical characteristics of a MOSFET-structured silicon field emitter by employing Maxwell 2D and Silvaco simulators. The potential distribution is obtained by Maxwell 2D simulator and the field emission current is calculated by Fowler-Nordheim equations. The characteristics of MOSFET is simulated by Silvaco simulator. Simulated results are almost identical to the experimental results. Also, we have studied the emission characteristics as funtions of several geometric parameters.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.1 s.244
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• pp.41-47
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• 2006

High resolution dopant profiling in semiconductor devices has been an intense research topic because of its practical importance in semiconductor industry. Although several techniques have already been developed. it still requires very expensive tools to achieve nanometer scale resolution. In this study we demonstrated a novel dopant profiling technique with nanometer resolution using very simple setup. The newly developed technique measures the thermoelectric voltage generated in the contact point of the SPM probe tip and MOSFET surface instead of electrical signals widely adopted in previous techniques like Scanning Capacitance Microscopy. The spatial resolution of our measurement technique is limited by the size of contact size between SPM probe tip and MOSFET surface and is estimated to be about 10 nm in this experiment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.77-83
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• 1994

In this paper we numerically approximated the field-effect mobility of a-Si:H TFT. Field-effect mobility, based on the charge-trapping model and new effective capacitance model in our study, used Chebyshev approximation was approximated as the function of gate potential(gate-to-channel voltage). Even though various external factors are changed, this formula can be applied by choosing the characteristic coefficients without any change of the approximation formula corresponding to each operation region. Using new approximated field-effect mobility formula, the dependences of field-effect mobility on materials and thickness of gate insulator, thickness of a-Si bulk, and operation temperature in inverted staggered-electrode a-Si:H TFT were estimated. By this was the usefulness of new approximated mobility formula proved.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.565-565
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• 2012

그래핀(Graphene) 기반의 전계효과 트랜지스터(Field effect transistor) 응용에 있어, 가장 핵심적인 도전과제중 하나는 에너지 밴드갭(Energy bandgap)을 갖는 그래핀 채널의 제작이다. 그래핀은 에너지 밴드갭이 존재하지 않는 반금속(semi metal)의 특성을 지니고 있어, 그 본래의 물리적 특성을 지니고서는 소자구현에 어려움이 있다. 그러나 폭이 수~수십 나노미터인 그래핀 나노리본(Graphene nanoribbon)의 경우 양자구속효과(Quantum confinement effect)에 의하여 에너지 밴드갭이 형성되며, 갭의 크기는 리본의 폭에 반비례한다는 연구결과가 보고된 바 있다. 이러한 이유에서, 효과적이며 실현가능한 그래핀 나노리본의 제작은 필수적이다. 본 연구에서는 은 나노 와이어(Ag nanowire)를 기반으로 한 그래핀 나노리본의 합성을 연구하였다. 은 나노와이어를 열화학 기상증착법(Thermal chemical vapor deposition)을 이용, 아세틸렌(Acetylene, C2H2) 가스를 탄소공급원으로 하여 그래핀을 나노와이어 표면에 합성하였다. 합성과정에서 구조에 영향을 미치는 요인인 합성온도와 가스의 비율, 압력 등을 조절하여 최적화된 합성조건을 확립하였다. 합성된 나노리본의 특성을 라만분광법(Raman spectroscopy)과 주사전자 현미경(Scanning electron microscopy), 투과전자현미경(Transmission electron microscopy), 원자힘 현미경(Atomic force microscopy)를 통하여 분석하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.381-382
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• 2018

Subthreshold swings (SSs) and on-currents of four types of junctionless nanowire tunnel field-effect transistor(JLNW-TFET) are observed. Ge-Si structure for the source-channel junction has the highest drive current among Si-Si, Si-Ge, and Ge-Ge junction, and the drive current increases up to 1000 times compared to others. Minimum SS of Si-Si junction is reduced by up to 5 times more than others.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.63-69
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• 2011

In this study, we report on the novel lithographic patterning method to fabricate organic thin film field effect transistors (OTFTs) based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30 nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce $Al_2O_3$ film grown via atomic layer deposition method onto pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated micron sized pentacene FETs and measured their electrical characteristics.