• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.87-94
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• 2005

In this paper a low-power DWT(Discrete Wavelet Transform) design technique is proposed. As basic low-pass filter for analysis bank, comb filter is utilized, and in order to improve frequency response for the comb filter, a fourth order polynomial is also proposed. Another filters are designed by using perfect reconstruction conditions. The lowpass filter coefficients of the analysis filter bank are optimized based on the cost function and perfect reconstruction condition. The number of the multiplications and MSE(Mean Squared Error) performance of the proposed DWT filter bank are compared with those of the JPEG2000 (9, 7) filter bank. It is shown that number of multiplications of the proposed filter bank are saved with 33.3%, and MSE values of the proposed filter bank are also superior to those of the JPEG2000 (9, 7) filter bank.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.26-27
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• 2010

기존의 역률 보상 회로(PFC 회로)는 저전압 입력 시에 정류 다이오드의 도통손실 증가로 인해 효율 상승에 제약을 받는다. Bridgeless PFC 컨버터는 입력 측의 정류 다이오드 없이 능동 스위치가 정류 동작을 수행하도록 하여 더 높은 효율을 얻을 수 있다. 본 논문에서는 고효율을 위한 새로운 절연형 bridgeless PFC 컨버터를 제안한다. 제안한 회로는 입력단의 정류 다이오드를 제거함으로써 도통 손실을 줄여 효율 향상을 꾀하였다. 또한 변압기를 사용하여 입출력 전압 이득 설계를 자유롭게 하였으며, 2차 DC/DC 컨버터 설계 시 절연이 필요하지 않도록 하였다. 제안한 회로의 성능을 65W급 프로토타입 컨버터의 실험을 통해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.665-670
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• 2016

In this paper, we suggest the design of OP-AMP using MOSFET in the operation of sub-threshold condition as a basic unit of an IoT. The sub-threshold operation of MOSFET is useful for an ultra low power consumption of sensor network system in the IoT, because it cause the supply voltage to be reduced. From the simulation result using 0.35 um CMOS process, the supply voltage, VDD can be reduced with 0.6 V, open-loop gain of 43 dB and the power consumption was evaluated with about $1.3{\mu}W$ and the active size for an integration was measured with $64{\mu}m{\times}105{\mu}m$. It is expected that the proposed circuit is applied to the low power sensor network for IoT.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.185-188
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• 2008

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.85-86
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• 2011

철도운영효율 향상을 위하여 첨단 기술을 기반으로 하는 스마트 철도 기술에 대한 개발 및 실용화 사업이 전 세계적으로 진행중에 있다. 철도의 수송력 증대와 운영비용 감소 및 시스템 변경 용이성등의 장점을 극대화하기 위하여 기존의 궤도회로 중심의 열차제어 시스템에서 통신기술을 기반으로 하는 열차제어시스템으로의 전환을 위한 많은 연구가 이루어지고 있다. 본 논문에서는 CBTC 시스템에서 GPS시스템의 적용 타당성 여부를 검증하였고 CBTC 시스템에서의 위치 정보 수신을 위한 GPS 수신데이터의 정합 알고리듬에 관한 저전력 분할 연산 알고리듬을 설계하여, 본 논문에서 제안한 코드는 기존의 수신데이터의 정합알고리듬 대비 2% 면적이 감소하는 것을 확인할 수 있었으며, 또한 전력소모가 7% 감소되는 것을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.50-55
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• 2008

As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.26-32
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• 2017

This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.