• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.193-199
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• 2011

In this paper, we proposed battery driven low power algorithm in mobile device. Algorithm the mobile devices in power of the battery for the task to perform power consumption to reduce the frequency alters. Power of the battery perform to a task power consumption of is less than the task perform to frequency the lower. Frequency control the task, depending on in the entire system devices used among the highest frequency with devices first target perform to. Frequency in the decrease the second largest frequency with of the device the frequency in changes the power consumption to calculate. The calculated consumption power the battery of level is greater than level the frequency by adjusting power consumption, lower power of the battery the task perform when you can to the frequency to adjust. Experiment the frequency by adjusting power consumption a method to reduce using [6] and in the same environment power of the battery consider the task to perform frequency were controlled. The results in [6] perform does not battery power on task operates that the result was.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.535-537
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• 2004

최근 센서 네트워크에 대한 필요성이 증대되면서 센서 기술과 통신 기술 등 센서 네트워크의 기반기술에 대한 연구가 활발하게 진행되고 있다. 특히, 센서 네트워크에서 센서 노드의 수명은 센서의 배터리 전력량에 비례하므로 보다 적은 전력으로 통신을 수행하는 기술들에 관심이 집중되고 있다. 이러한 저전력 통신 프로토콜 가운데 대표적인 것이 시간 분할 다중 접속(TDMA) 기반 MAC 프로토콜이다. 지정된 시간에만 센서 노드의 통신 상태를 정지(sleep)상태에서 유휴(idle)상태로 변경하여 통신을 수행하므로 전력 소비를 최소화시키는 기술이다. 그러나 이웃한 다른 센서들 간의 통신을 간섭하지 않기 위해 센서들은 통신시 서로 다른 주파수를 사용해야 한다. 이러한 제한 사항을 충족시키기 위해서는 센서 노드들이 다양한 주파수를 청취할 수 있어야 하며. 이는 센서 노드 생산시 제조단가의 증가와 직결되어 센서 네트워크의 상용화에 주요한 문제가 될 수 있다. 따라서 본 논문에서는 시간 분할접속(TDMA) 기반 저전력 MAC 프로토콜에서 단일 주파수를 사용한 수 있도록 통신 시간(time slot)을 할당하는 알고리즘을 제안하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1702-1708
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• 2013

OLED has good efficiency of power consumption by having no power consumption from black color as different with LCD. when it has white color, all RGB pixel should be glowing with high power consumption and that can make it has short life time. This paper suggest the way of low power consumption for OLED panel using adaptive luminance enhancement with color compensation and implement it as hardware. This way which is based on luminance information of input image makes converted luminance value from each pixel in real time. There is with using the basic idea of chromaticity reduction algorithm, showing new algorithm of color correction. And performance of proposed method was confirmed by comparing the conventional method in experiments about 48.43% current reduction. The proposed method was designed by Verilog HDL and was verified by using OpenCV and Windows Program.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.3
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• pp.95-99
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• 2008

This paper proposes a new minimal resource high-level synthesis algorithm for low power design automation. The proposed algorithm executes an efficient approach to minimize the power consumption of the functional units in a circuit during the high level synthesis. In this paper, we visit all control steps one by one to reduce the switching activity in CDFG. The register sharing algorithm determines the minimum register after the life time analysis of all variable. According to property of input signal for functional unit, the proposed method visits all control step one by one and determines the resource allocation with minimal power consumption at each control step in a greedy fashion. The effect of the proposed algorithm has been proved through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low rover.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.875-877
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• 2015

IoT 환경의 센서 네트워크와 RFID 태그 등에서의 AES나 SEED에 대응 할 수 있는 새로운 저전력 경량화 암호 알고리즘이 필요 해짐에 따라 본 논문에서는 2006년 국내에서 제안된 HIGHT와 2007년 CHES에서 제안된 PRESENT 알고리즘을 Arduino에 적용하여 성능을 비교분석 하였다. 그 결과 HIGHT 알고리즘이 PRESENT알고리즘에 비하여 더 짧고, 적은 수행시간과 프로그램 메모리 사용량을 보였으며, 더 많은 동적 메모리 사용량을 보였다.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Journal of the Korea Society of Computer and Information
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• v.15 no.5
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• pp.103-111
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• 2010

This paper proposes an efficient data transmission strategy using adaptive-tier low transmission power schedule in a TDMA-based ad hoc MAC protocol. Since the network resource of ad hoc networks has the characteristic of reassignment due to the multiple interferences and the contention-based limited wireless channel, the efficient time slot assignment and low power transmission scheme are the main research topics in developing ad hoc algorithms. Based on the proposed scheme of interference avoidance when neighbor clusters transmit packets, this paper can minimize the total energy dissipation and maximize the utilization of time slot in each ad hoc node. Simulation demonstrates that the proposed algorithm yields 15.8 % lower energy dissipation and 4.66% higher time slot utilization compared to the ones of two-tier conventional energy dissipation model.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.179-188
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• 2003

Advances in wireless networking technology has engendered a new paradigm of computing, called mobile computing, in which users carrying portable devices have access to a shared infrastructure independent of their physical locations. Wireless communication has some restraints such as disconnection, low bandwidth, a variation of available bandwidth, network heterogeneity, security risk, small storage, and low power. Power adaptation routing scheme overcome the shortage of power by adjusting the output power, was proposed. Existing power saving routing algorithm has some minor effect such as seceding from shortest path to minimize the power consumption, and number of nodes that Participate in routing than optimal because it select a next node with considering only consuming power. This paper supplements the weak point in the existing power saving routing algorithm as considering the gradual approach to final destination and the number of optimal nodes that participate in routing.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.503-509
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• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.