• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.3
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• pp.95-103
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• 2007

Portable multimedia Player (PMP) devices have been gaining in its popularity with the emerging digital convergence of data, video, audio, etc. Since the PMP devices are typically equipped with DSP, a bigger LCD screen, and a hard disk, efficient power management has become more crucial than the other portable devices. This paper builds up a hardware/software-based power measurement system based on data acquisition devices. Subsequently, it measures and analyzes the power consumed in commercial PMP devices under different types of events: the system boot & shutdown, video playback, and the use of different video-coding types. Finally, our analysis of the measured power consumption patterns reveals useful information for the design of low-power PMP devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.497-500
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• 2018

데이터 센터를 기반으로 서비스를 수행하는 기업들은 비용절감을 위해 서버 가상화 기술을 이용한다. 서버 가상화를 이용하는 기업들은 대부분 하이퍼바이저 기반의 서버 가상화 기술을 사용하며, 이 경우 하드웨어 가상화를 통해 커널 단에서 많은 I/O와 리소스를 처리해야 한다. 따라서 하이퍼바이저 기반의 서비스는 느리다는 단점이 있으며 이를 해결하기 위해 컨테이너 기반의 가상화 기술을 이용할 수 있다. 하지만 컨테이너 기반의 네트워크 또한 문제점이 존재한다. 컨테이너 기반의 네트워크는 유연한 네트워크를 구성하기 어렵고, 기존의 컨테이너 네트워크 인터페이스를 활용할 경우 데이터 전송 성능이 저하된다. 본 논문에서는 컨테이너 오케스트레이션 툴인 Kubernetes와 SDN (Software-Defined Network) 기반의 가상전용 네트워크 연계 환경을 구축하고 이에 적합한 컨테이너 네트워크를 연구하여 이의 문제점을 해결한다. 즉, 가상전용 네트워크와 Kubernetes의 연계를 통해 고성능의 유연한 네트워크를 구성할 수 있는 프레임워크를 개발하여 기존 컨테이너 기반 네트워크와 비교하고 성능을 검증했다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.97-102
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• 2007

In this paper, a new architecture for fast-serial $GF(2^m)$ multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.103-112
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• 2007

In this paper, we implement a hypervisor that runs multiple uC/OS-II real-time kernels on one microprocessor. The hypervisor virtualizes microprocessor and memory that are main resources managed by uC/OS-II kernel. Microprocessor is virtualized by controlling interrupts that uC/OS-II real-time kernel handles and memory is virtualized by partitioning physical memory. The hypervisor consists of three components: interrupt control routines that virtualize timer interrupt and software interrupt, a startup code that initializes the hypervisor and uC/OS-II kernels, and an API that provides communication between two kernels. The original uC/OS-II kernel needs to be modified slightly in source-code level to run on the hypervisor. We performed a real-time test and an independent computation test on Jupiter 32-bit EISC microprocessor and showed that the virtualized kernels run without problem. The result of our research can reduce the hardware cost, the system space and weight, and system power consumption when the hypervisor is applied in embedded applications that require many embedded microprocessors.

• Journal of Digital Convergence
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• v.13 no.8
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• pp.245-251
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• 2015

If a digital signage system is operated in PC mounted in the Window OS then the implementing price is very high. For resolving this problem, we used the Smartphone mounted in ARM Cortex family of multi-core processor-based mobile platform. We developed a low-power low-cost digital signage system and a remote convergence content management program based on web server. This convergence system manages advertising content to a remote control device anywhere using remote control technology. This system is one integrated system with display and is a low-power consumed and is developed in very efficient hardware interface. And condition sensors(intensity of illumination, temperature, weather, GPS etc) is equipped in the developed system. Automatic contents builder and Context-aware SMIL module is also implemented in the convergence system. We achieved over 50% power savings comparing with conventional Window OS system and 16 points multi-touch in our system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.