• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.24-30
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. The probability of defect occurence on spare lines has been increased through the growth of the density of recent memories with 2 dimensional spare architecture. In this paper, a new analysis region virtualization scheme is proposed. the analysis region virtualization scheme can be applied with any BIRA (built-in redundancy analysis) algorithms without the loss of their repair rates. The analysis region virtualization scheme can be a viable solution for BIRA considering the faulty spare lines of the future high density memories.