• Journal of Biomedical Engineering Research
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• v.31 no.5
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• pp.385-394
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• 2010

Automatic gain control(AGC) is used in hearing aids to compensate for the hearing level as to reduced dynamic range. AGC is consisted of the main 4 factors which are compression threshold, compression ratio, attack time, and release time. This study especially focus on each individual need for optimum release time parameters that can be changed within 7 certain range such as 12, 64, 128, 512, 2094, and 4096ms. To estimate the effect of various release time in AGC, twelve normal hearing and twelve hearing impaired listeners are participated. The stimuli are used by one syllable and sentence which have the same acoustic energy respectively. Then, each of score of the word recognition score is checked in quiet and noise conditions. As a result, it is verified that most people have the different best recognition score on specific release time. Also, if hearing aids is set by the optimum release time in each person, it is helpful in speech recognition and discrimination.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.89-96
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.831-835
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• 2016

In this paper, a dual-channel feed-forward transimpedance(TIA) array is realized in a standard $0.18-{\mu}m$ CMOS technology which exploits automatic gain control function to provide 40-dB input dynamic range for either detecting targets nearby or sensing imminent danger situations. Compared to the previously reported conventional feed-forward TIA, the proposed automatic-gain-control feed-forward TIA(AFF-TIA) extends the input dynamic range 25 dB wider by employing a 4-level automatic gain control circuit. Measured results demonstrate the linearly varying transimpedance gain of 47 to $72dB{\Omega}$, input dynamic range of 1:100, the bandwidth of $${\geq_-}670MHz$$, the equivalent input referred noise current spectral density of 6.9 pA/${\surd}$HZ, the maximum sensitivity of -26.8 dBm for $10^{-12}BER$, and the power consumption of 27.6 mW from a single 1.8-V supply. The dual-channel chip occupies the area of $1.0{\times}0.73mm^2$ including I/O pads.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.219-226
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• 2000

In this paper, we design and implement a IF(intermediate frequency) module for WLL(wireless local loop) CDMA(code division multiple access) basestation. The implemented IF transceiver is consists of transmitter, receiver and local oscillator. The considered signal bandwidth is 10 MHz and the local carrier frequency is 40 MHz. As test results, the If transmitter output power is -5dBm $\pm3dB$when the baseband input is -10dBm $\pm3dB$, and the IF receiver output power is -10dBm $\pm3dB$when the IF input is -5dBm $\pm3dB$. Also the AGC(automatic gain control) circuit has dynamic range of 9 dB from -7dBm to +2dBm with output power 2dBm. And the group delay characteristic is analyzed by comparing the phase delay from 1 MHz to 5 MHz and the phase distortion is very low. We can conclude that this IF system can be applied to high speed data rate communication system.

• Journal of Advanced Navigation Technology
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• v.25 no.1
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• pp.68-77
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• 2021

In this paper, a GPS/MEMS IMU integrated navigation receiver module capable of operating in a high dynamic environment is designed and fabricated, and the results is confirmed. The designed module is composed of RF receiver unit, inertial measurement unit, signal processing unit, correlator, and navigation S/W. The RF receiver performs the functions of low noise amplification, frequency conversion, filtering, and automatic gain control. The inertial measurement unit collects measurement data from a MEMS class IMU applied with a 3-axis gyroscope, accelerometer, and geomagnetic sensor. In addition, it provides an interface to transmit to the navigation S/W. The signal processing unit and the correlator is implemented with FPGA logic to perform filtering and corrrelation value calculation. Navigation S/W is implemented using the internal CPU of the FPGA. The size of the manufactured module is 95.0×85.0×.12.5mm, the weight is 110g, and the navigation accuracy performance within the specification is confirmed in an environment of 1200m/s and acceleration of 10g.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.64-68
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• 2007

This paper describes the development of RF front.end equipment of a wide band high precision satellite navigation receiver to be able to receive the currently available GPS navigation signal and the GALILEO navigation signal to be developed in Europe in the near future. The wide band satellite navigation receiver with high precision performance is composed of L - band antenna, RF/IF converters for multi - band navigation signals, and high performance baseband processor. The L - band satellite navigation antenna is able to be received the signals in the range from 1.1 GHz to 1.6 GHz and from the navigation satellite positioned near the horizon. The navigation signal of GALILEO navigation satellite consists of L1, E5, and E6 band with signal bandwidth more than 20 MHz which is wider than GPS signal. Due to the wide band navigation signal, the IF frequency and signal processing speed should be increased. The RF/IF converter has been designed with the single stage downconversion structure, and the IF frequency of 140 MHz has been derived from considering the maximum signal bandwidth and the sampling frequency of 112 MHz to be used in ADC circuit. The final output of RF/IF converter is a digital IF signal which is generated from signal processing of the AD converter from the IF signal. The developed RF front - end has the C/N0 performance over 40dB - Hz for the - 130dBm input signal power and includes the automatic gain control circuits to provide the dynamic range over 40dB.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.