• Title/Summary/Keyword: 자가복구

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The Development on Distribution Facility Location Tracking System using a technique of GPS (GPS를 이용한 배전계통 현장위치파악 장치개발)

  • Jung, Geum-Young;Oh, Young-Hyun;Park, Sung-Chul
    • Proceedings of the KIEE Conference
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    • 2005.11b
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    • pp.107-109
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    • 2005
  • NDIS 환경에서 GPS 및 자가 무선통신 전국망을 이용하여 체계적이고 신속한 고장복구를 지원할 수 있는 배전기동보수시스템 연구개발에 있어 안전사고 예방 및 한 차원 높은 서비스 제공을 위한 음성안내 시스템의 개발에 대해 논하고자 한다.

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An Automated Approach to Monitoring External Resource for Self-Healing (자가 치유를 위한 외부 자원 모니터 자동 생성 기법)

  • Lee, Hee-Won;Lee, Joon-Hoon;Jung, Jin-Soo;Park, Jeong-Min;Lee, Eun-Seok
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.10b
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    • pp.38-43
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    • 2007
  • 최근의 소프트웨어들이 다양한 기능을 갖추어가면서 점차 복잡도가 증가하고 있으며, 이에 따라 오류로부터의 복구도 어려워져 가고 있다. 이러한 변화는 소프트웨어의 자가 치유 연구에 중요한 이슈가 되고 있다. 하지만 자가 치유 방법론에서 중요한 요소 중에 하나인 모니터는 아직까지 개발자가 일일이 작성해야 하는 한계가 있다. 따라서 본 논문은 외부 자원으로 인한 오류를 탐지하는 모니터 모듈의 생성을 자동화하는 방법론을 제시하고, 이것을 적용한 소프트웨어 아키텍처를 제안한다. 본 방법론은 1) UML의 배치 다이어그램으로부터 소프트웨어와 하드웨어간의 연결을 분석하고, 2) 기술된 제약사항을 이용하여 모니터링 모듈을 자동으로 생성한다. 3) 이후 생성된 모듈을 소프트웨어 사양에 맞게 수정한 후 컴포넌트에 추가한다. 이러한 제안 방법론을 통해 기존에 수동으로 만들어야 했던 외부 자원 모니터를 자동화하는 것이 가능해 진다. 본 논문에서는 평가를 위해 제안 방법론을 비디오 회의 시스템의 클라이언트에 적용하여, 외부 자원의 오류를 올바르게 탐지해내는지 확인한다.

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An Predictive Analytics based on Goal-Scenario for Self-adaptive System (자가적응형 시스템을 위한 목표 시나리오 기반 예측 분석)

  • Baek, Su-Jin
    • Journal of the Korea Convergence Society
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    • v.8 no.11
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    • pp.77-83
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    • 2017
  • For efficient predictive analysis, self-healing research is needed that enables the system to recover autonomously by self-cognition and diagnosing system problems. However, software development does not provide formal contextual information analysis and appropriate presentation structure according to external situation. In this paper, we propose a prediction analysis method based on the change contents by applying the extraction rule to the functions that can act, data, and transaction based on the new Goal-scenario. We also evaluated how well the predictive analysis met through the performance indicators for achieving the requirements goal. Compared with the existing methods, the proposed method has a maximum 32.8% higher matching result through performance measurement, resulting in a 28.9% error rate and a 45.8% reduction in the change code. This shows that it can be processed into a serviceable form through rules, and it shows that performance can be expanded through predictive analysis of changes.

Automatic Recovery and Reset Algorithms for System Controller Errors

  • Lee, Yon-Sik
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.3
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    • pp.89-96
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    • 2020
  • Solar lamp systems may not operate normally in the event of some system or controller failure due to internal or external factors, in which case secondary problems occur, which may cost the system recovery. Thus, when these errors occur, a technology is needed to recover to the state it was in before the failure occurred and to enable re-execution. This paper designs and implements a system that can recover the state of the system to the state prior to the time of the error by using the Watchdog Timer within the controller if a software error has occurred inside the system, and it also proposes a technology to reset and re-execution the system through a separate reset circuit in the event of hardware failure. The proposed system provides stable operation, maintenance cost reduction and reliability of the solar lamp system by enabling the system to operate semi-permanently without external support by utilizing the automatic recovery and automatic reset function for errors that occur in the operation of the solar lamp system. In addition, it can be applied to maintain the system's constancy by utilizing the self-operation, diagnosis and recovery functions required in various high reliability applications.

Electric Power System Relay Protection System Design for the Proton Accelerator Research Center of PEFP (양성자가속기 연구센터의 전력계통 보호계전 방식)

  • Mun, Kyeong-Jun;Lee, Seok-Ki;Jeon, Gye-Po;Cho, Jin-Sam;Min, Yi-Sub;Nam, Jung-Min;Kim, Jun-Yeon
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.428_429
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    • 2009
  • 전력계통 운용시 고장이 발생하면 계통 운전원은 계전기 및 차단기 관련 동작정보 및 경보로부터 해당 고장내용을 판단하고 계통복구를 위한 조작을 행한다. 본 논문에서는 현재 건설중인 양성자가속기 연구센터의 전력 계통 운용시 발생한 고장에 따른 다중경보신호를 분석하기 위하여 전력계통의 고장영역별로 동작하는 보호계전기 신호, 차단기 신호 및 경보신호를 분류함으로써 이를 향후 전력계통 운용시 고장진단을 위한 기초자료로 활용하고자 한다.

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An Optimal Scrubbing Scheme for Auto Error Detection & Correction Logic (자가 복구 오류 검출 및 정정 회로 적용을 고려한 최적 스크러빙 방안)

  • Ryu, Sang-Moon
    • Journal of Institute of Control, Robotics and Systems
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    • v.17 no.11
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    • pp.1101-1105
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    • 2011
  • Radiation particles can introduce temporary errors in memory systems. To protect against these errors, so-called soft errors, error detection and correcting codes are used. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU's writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.

The methods of error detection at Digital circuit using the FPGA 2-dimensional array (FPGA 2 차원 배열을 사용한 디지털 회로에서 오류 검출의 방법)

  • Kim, Soke-Hwan;Hur, Chang-Wu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.202-206
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    • 2012
  • In this paper, we proposed on the direction of self-repairing mimicking the cell on the digital system design. Three-dimensional array of cells rather than using the original structure of FPGA, an array of blocks for efficient error detection methods were investigated. With a certain regularity, so the design method in detail by dividing the full array. The digital circuits can be detected fault location easily and quickly.

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Built-In Redundancy Analysis Algorithm for Embedded Memory Built-In Self Repair with 2-D Redundancy (내장 메모리 자가 복구를 위한 여분의 메모리 분석 알고리즘)

  • Shim, Eun-Sung;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.113-120
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    • 2007
  • With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

A Fault Detection and Self-Recovery System for Space-Borne Dual Ring Counters (우주용 중복구조 링 카운터를 위한 고장 진단 및 자가 복구 시스템)

  • Kwak, Seong Woo;Yang, Jung-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.1
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    • pp.120-126
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    • 2013
  • This paper proposes a novel scheme of fault detection and self-recovery for space-borne dual ring counters subject to transient faults. The considered ring counter is equipped with hardware redundancy, but it has a limited output domain where direct access to the current state is unavailable. We employ the theory of corrective control to detect any transient fault occurring to the counter bits and to realize immediate self-recovery of the ring counter back to the normal state. The structure of the fault-tolerant controller is designed to be minimal regardless of the counter size. To validate the applicability, we implement the proposed system on a commercial FGPA board.

Programmable Memory BIST and BISR Using Flash Memory for Embedded Memory (내장 메모리를 위한 프로그램 가능한 자체 테스트와 플래시 메모리를 이용한 자가 복구 기술)

  • Hong, Won-Gi;Choi, Jung-Dai;Shim, Eun-Sung;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.69-81
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    • 2008
  • The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.