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Comparative Analysis and Performance Evaluation of New Low-Power, Low-Noise, High-Speed CMOS LVDS I/O Circuits (저 전력, 저 잡음, 고속 CMOS LVDS I/O 회로에 대한 비교 분석 및 성능 평가)

  • Byun, Young-Yong;Kim, Tae-Woong;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.2
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    • pp.26-36
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    • 2008
  • Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

Design of a Inverter-Based 3rd Order ΔΣ Modulator Using 1.5bit Comparators (1.5비트 비교기를 이용한 인버터 기반 3차 델타-시그마 변조기)

  • Choi, Jeong Hoon;Seong, Jae Hyeon;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.39-46
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    • 2016
  • This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

A Frequency Synthesizer for MB-OFDM UWB with Fine Resolution VCO Tuning Scheme (고 해상도 VCO 튜닝 기법을 이용한 MB-OFDM UWB용 주파수 합성기)

  • Park, Joon-Sung;Nam, Chul;Kim, Young-Shin;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.117-124
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    • 2009
  • This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

Indoor Environment Control System based EEG Signal and Internet of Things (EEG 신호 및 사물인터넷 기반 실내 환경 제어 시스템)

  • Jeong, Haesung;Lee, Sangmin;Kwon, Jangwoo
    • Journal of rehabilitation welfare engineering & assistive technology
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    • v.11 no.1
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    • pp.45-52
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    • 2017
  • EEG signals that are the same as those that have the same disabled people. So, the EEG signals are becoming the next generation. In this paper, we propose an internet of things system that controls the indoor environment using EEG signal. The proposed system consists EEG measurement device, EEG simulation software and indoor environment control device. We use data as EEG signal data on emotional imagination condition in a comfortable state and logical imagination condition in concentrated state. The noise of measured signal is removed by the ICA algorithm and beta waves are extracted from it. then, it goes through learning and test process using SVM. The subjects were trained to improve the EEG signal accuracy through the EEG simulation software and the average accuracy were 87.69%. The EEG signal from the EEG measurement device is transmitted to the EEG simulation software through the serial communication. then the control command is generated by classifying emotional imagination condition and logical imagination condition. The generated control command is transmitted to the indoor environment control device through the Zigbee communication. In case of the emotional imagination condition, the soft lighting and classical music are outputted. In the logical imagination condition, the learning white noise and bright lighting are outputted. The proposed system can be applied to software and device control based BCI.

Design of a step-up DC-DC Converter using a 0.18 um CMOS Process (0.18 um CMOS 공정을 이용한 승압형 DC-DC 컨버터 설계)

  • Lee, Ja-kyeong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.715-720
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    • 2016
  • This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

Computationally Efficient ion-Splitting Method for Monte Carlo ion Implantation Simulation for the Analysis of ULSI CMOS Characteristics (ULSI급 CMOS 소자 특성 분석을 위한 몬테 카를로 이온 주입 공정 시뮬레이션시의 효율적인 가상 이온 발생법)

  • Son, Myeong-Sik;Lee, Jin-Gu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.11
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    • pp.771-780
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    • 2001
  • It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

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Design and Experiment of Ku_band Linear Active Phased Array Antenna System (Ku 대역 선형 능동 위상 배열 안테나 시스템 설계 및 실험)

  • Ryu Sung-Wook;Eom Soon-Young;Yun Jae-Hoon;Jeon Soon-Ick;Kim Nam
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.7 s.110
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    • pp.694-705
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    • 2006
  • In this paper, the linear active phased array antenna system operated in Ku DBS band was designed and experimented. The antenna system was composed of sixteen radiating active channels and Wilkinson power combiners with 16-channel inputs, a stabilizing DC bias and phase control board. Electrical beams of the antenna system can be formed by controling the phase-states of 3-bit digital phase shifter inside each active channel by virtue of the phase control board. The amplitude and phase deviations measured between active channels were less than ${\pm}0.8dB$ and ${\pm}15^{\circ}$, respectively, and the noise figure of each active channel was measured less than 1.2 dB in the operating band. The measured performances of the overall antenna system showed the antenna gain of more than 23.07 dBi and the sidelobe level of less than -11.17 dBc, and the bore-sight cross-polarization level of less than -12.75 dBc in the operating band. Also, by phase-controlling active channels, the beam scan patterns at $10^{\circ},\;20^{\circ},\;30^{\circ}$ were measured, and the losses caused by the corresponding beam scanning were 1.1 dB, 2.5 dB and 3.6 dB from the measurements, respectively.

Evaluation of a signal segregation by FDBM (FDBM의 음원분리 성능평가)

  • Lee, Chai-Bong
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.12
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    • pp.1793-1802
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    • 2013
  • Various approaches for sound source segregation have been proposed. Among these approaches, frequency domain binaural model(FDBM) has the advantages of low computational load and effective howling cancellation. A binaural hearing assistance system based on FDBM has been proposed. This system can enhance desired signal based on the directivity information. Although FDBM has been evaluated in terms of signal-to-noise ratio (SNR) and coherence function, the evaluation results do not always agree with the human impressions. These evaluation methods provide physical measures, and do not take account of perceptual aspect of human being. Considering a binaural hearing assistance system as a one of major applications, the quality of segregated sound should keep level enough. In the paper, signal segregation performance by means of FDBM is evaluated by three objective methods, i.e., SNR, coherence and Perceptual Evaluation of Speech Quality(PESQ), to discuss the characteristic of FDBM on the sound source segregation performance. The simulation's evaluation results show that FDBM improves the quality of the left and right channel signals to an equivalent level. And the results suggest the possibility that PESQ provides a more useful measure than SNR and coherence in terms of the segregation performance of FDBM. The evaluation results by PESQ show the effects from segregation parameters and indicate appropriate parameters under the conditions. In the paper, signal segregation performance by means of FDBM is evaluated by three objective methods, i.e., SNR, coherence and PESQ, to discuss the characteristic of FDBM on the sound source segregation performance. The simulation's evaluation results show that FDBM improves the quality of the left and right channel signals to an equivalent level. And the results suggest the possibility that PESQ provides a more useful measure than SNR and coherence in terms of the segregation performance of FDBM. The evaluation results by PESQ show the effects from segregation parameters and indicate appropriate parameters under the conditions.

DESIGN AND DEVELOPMENT OF MULTI-PURPOSE CCD CAMERA SYSTEM WITH THERMOELECTRIC COOLING I. HARDWARE (열전냉각방식의 범용 CCD 카메라 시스템 개발 I. 하드웨어)

  • Kang, Y.W.;Byun, Y.I.;Rhee, J.H.;Oh, S.H.;Kim, D.K.
    • Journal of Astronomy and Space Sciences
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    • v.24 no.4
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    • pp.349-366
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    • 2007
  • We designed and developed a multi-purpose CCD camera system for three kinds of CCDs; KAF-0401E($768{\times}512$), KAF-1602E($1536{\times}1024$), KAF-3200E($2184{\times}1472$) made by KODAK Co.. The system supports fast USB port as well as parallel port for data I/O and control signal. The packing is based on two stage circuit boards for size reduction and contains built-in filter wheel. Basic hardware components include clock pattern circuit, A/D conversion circuit, CCD data flow control circuit, and CCD temperature control unit. The CCD temperature can be controlled with accuracy of approximately $0.4^{\circ}C$ in the max. range of temperature, ${\Delta}33^{\circ}C$. This CCD camera system has with readout noise $6\;e^-$, and system gain $5\;e^-/ADU$. A total of 10 CCD camera systems were produced and our tests show that all of them show passable performance.

The Developed Study for SMPS to Protect the Noise and Inrush Current at LED Lighting Source (LED 광원에서 잡음 및 돌입전류 방지를 위한 스위칭모드 전원공급 장치 (SMPS) 개발 연구)

  • Chung, Chansoo;Hong, Gyujang;We, Sungbok;Yu, Geonsu;Kim, Mijin
    • KEPCO Journal on Electric Power and Energy
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    • v.2 no.4
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    • pp.577-582
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    • 2016
  • This Study focused on the development of SMPS (Switching Mode Power Supply) to supply the constant votage and current nevertheless LED fluorescent Light generated the electric noise (with Harmonics) and Inrush current at instant time of turn-on and off. Recently, according to the Green policy in government, the LED fluorescent Lighter showed the rapidly increasing tend as indoor and outdoor Lighter. But, because of costs, LED fluorescent Light not considered and neglected the following items; power factor, efficiency, Harmonics and Inrush current. So, we are developed the SMPS about 3 key issues as follows: 1st, power factor and efficiency is 85%. 2nd, the switching noisy by harmonic is minimized. 3rd, the Inrush current at turn on and off time is reduced the minimum 0.3 A after $100{\mu}sec$ on turnon time. The proposed SMPS adjusted by LNK 409 driver (included the high frequency modulation function). Although, the developed SMPS maintained the about 85% of power factor and efficiency. but, the SMPS must be generated low heat by the variation of minute load current at switching timing. To improve the above weak point, the developed SMPS have the feedback monitoring circuit between input side and output side to maintain the power factor and efficiency. Also, we are studied the time-constant of control circuit to output the constant voltage and current nevertheless the load disturbance of LED lighting. The LED fluorescent Light of 46W is checked the above items.