• Title/Summary/Keyword: 입력포트

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Design of Contactless Power Transmission Device Using Cavity Resonator (공동공진기를 이용한 무접점 전력 전송 장치 설계)

  • Chang, Tae-Soon;Kim, Yong-Nam;Hur, Jung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.11
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    • pp.1025-1033
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    • 2011
  • In this paper, we introduce the contactless power transmission device for transmitting the power with the resonant characteristic of the cavity resonator. When transmitting the power, the contactless power transmission device begins to work in the condition where the transceiver adheres closely. The transceiver is electrically separated because there is no conductive terminal outside and the size of the receiver required for the electric power transmission can be minimized. The cavity resonator comprises slots for the input port and output port in the upper side conductor plate of the cavity and forms the input port and output port using the stripline structure at this upper part. The some of output port is separated from it and the electric power receiver is formed thus the union can be possible. The rest except electric power receiver become the electric power transmitter, which includes the input port of stripline-slot coupling, cavity, and the slot of the output port. If the transmitter and the receiver are combined, they become the form in which the electricity is transferred from the input port to the output port in a cavity resonator. The center frequency of the contactless power transmitter manufactured is 5.782 GHz. and $S_{21}$ is measured as -1.07 dB. It is confirmed that the high electric power transfer rate is approximately 78 %.

Self-Similarity of ATM Network Environment (ATM 네트워크 환경에서의 Self-Similarity 분석)

  • 김기완;김두용
    • Proceedings of the Korea Society for Simulation Conference
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    • 2002.05a
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    • pp.239-242
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    • 2002
  • 멀티미디어 환경에서 많은 패킷 스위치 네트워크로부터 발생되는 트래픽은 burstiness성질이 상당히 넓은 범위의 time scale상에 존재하고, 트래픽 특성이 self-similar현상을 보이고 있다는 것이 알려지고 있다. 본 논문에서는 Shared-Buffer를 이용한 ATM 스위치 buffer관리방법을 적용하여 입력포트에 self-similar 트래픽이 들어올 때 출력포트의 long-range dependency의 변화를 분석하며 아울러 큐잉 지연, 셀 손실률 그리고 이용도(utilization)등이 self-similar 트래픽에 미치는 영향을 분석할 것이다.

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Performance Analysis of Shared-Memory ATM switches in Self-Similar Traffic Environment (Self-Similar 트래픽 환경에서 공유 메모리를 갖는 ATM 스위치의 성능분석)

  • 김기완;김두용
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04d
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    • pp.235-237
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    • 2003
  • 멀티미디어 데이터 전송이 가능한 초고속 통신망의 발달로 음성을 위주로 서비스하던 과거와는 다른 self-similar 특성을 갖는 데이터 트래픽이 발생된다는 것이 알려지고 있다. 이러한 트래픽은 전통적인 네트워크 해석 방법인 포와송 트래픽 모델과는 상당히 차이가 난다는 것이 여러 트래픽의 측정 결과 나타나고 있다. 본 논문에서는 공유 메모리를 갖는 CS(Complete Sharing), DT(Dynamic Threshold), PO(Push-Out) 그리고, SMXQ(Sharing with Maximum Queue)와 같은 다양한 ATM(Asynchronous Transfer Mode) 스위치의 버퍼 관리 기법을 이용하여 입력포트에 self-similar 성질을 갖는 트래픽이 들어올 때 출력포트에서의 self-similarity와 셀 손실률 그리고, 이용률 등을 분석한다.

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Architecture of Multiple-Queue Manager for Input-Queued Switch Tolerating Arbitration Latency (중재 지연 내성을 가지는 입력 큐 스위치의 다중 큐 관리기 구조)

  • 정갑중;이범철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12C
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    • pp.261-267
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    • 2001
  • This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

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Design and Fabrication of DLP Array Antenna for 3.5 GHz Band (3.5 GHz 대역에서 동작하는 DLP 배열 안테나의 설계 및 제작)

  • Yoon, Joong-Han
    • The Journal of the Korea institute of electronic communication sciences
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    • v.16 no.6
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    • pp.1037-1044
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    • 2021
  • In this paper, we propose DLP(Dual Linear Polarization) array antenna for 3.5 GHz band. The proposed antenna has 1×4 array antenna and design two port network. A cross shape is inserted at the bottom of the patch for impedance matching. The size of each patch antenna is 18.85 mm(W1)×18.85 mm(L1), array antenna is designed on the FR-4 substrate, which is 236.0 mm(W)×60.2 mm(L), thickness (h) 1.6 mm, and the dielectric constant is 4.3. From the fabrication and measurement results, bandwidths of 70 MHz (3.54 to 3.61 GHz) for input port 1, 75 MHz (3.55 to 3.625 GHz) for input port 2 are obtained on the basis of -10 dB return loss and transmission coefficient S21 is under the -20 dB. Also, cross polarization between two port obtained.

Unequal Power Divider based on Adjustment Electrical Length of Uniform Transmission Line (단일 전송선로의 전기적 길이 조정을 이용한 비대칭 분배기)

  • Kwon, Sang-Keun;Kim, Young
    • Journal of Advanced Navigation Technology
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    • v.22 no.6
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    • pp.642-647
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    • 2018
  • In this paper, an unequal power divider based on adjusting electrical length of uniform transmission line is presented. This divider consists of three uniform transmission lines and one isolation resistor and have the different port impedances of input and output. The feature of proposed divider can changed the power dividing ratio to adjust only electrical length of uniform transmission lines. To verify the feasibility of proposed power divider, two divider circuits are designed, one is 1:2 power dividing ratio divider with $60{\Omega}$ uniform transmission line and $40{\Omega}$ input port impedances and $45{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.7 dB/ 5.0 dB, return losses of more than -30 dB and isolation of more than -35 dB. The other is 1:4 power dividing ratio divider with $40{\Omega}$ uniform transmission line and $50{\Omega}$ input port impedances and $75{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.3 dB/ 6.8 dB, return losses of more than -12 dB and isolation of more than -19 dB. The measured performance data agreed well with the simulated results.

THREE-DIMENSIONAL ROUND-ROBIN SCHEDULER FOR ADVANCED INPUT QUEUING SWITCHES (고속 입력큐 스위치 패브릭을 위한 3차원 라운드로빈 스케줄러)

  • Jeong, Gab-Joong;Lee, Bhum-Cheol
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.373-376
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    • 2003
  • This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

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Input Port re-allocation technique for the elimination of the internal blocking in banyan ATM switches (반얀망 ATM 스위치에서의 내부충돌 제거를 위한 입력 포트 재할당 기법)

  • 이주영;정준모;고광철;정재일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1124-1131
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    • 2002
  • The banyan network is a popular and basic structure of the multi-stage ATM switches. This paper presents a novel approach to resolve the internal blocking of the banyan network by using a Non-Blocking Permutation Generator (NBPG). The NBPG performs two functions, i.e., the first is to extract the conflict cells from the incoming cells and Ole second is to re-assign new input port addresses to the conflict cells. As a result, NBPG generates non-blocking I/O permutations. To estimate the performance of the NBPG, we provide the results of several simulations.

A study on control of generators based on SMPS (SMPS 기반 발전기 제어 시스템에 관한 연구)

  • Jeong, Yang-Kwon;Um, Tae-Hyoun;Kim, Gi-Hoon;Choi, Hyung-Ju
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.1
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    • pp.107-115
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    • 2012
  • This study incorporates welders and generators needed to use it and welder generators to be used as is to configure the system. Thus in order to propose an integrated system to prevent the rapid charging process to manage the power state information, system configuration is the most important. Therefore, the battery charging output port, the main input and output control ports, the generator control port, a warning alarm buzzer, UI switch input, EXT power output, check the battery status input, battery charge and discharge current, UI input control switch, generator status, the main power input and output, the output voltage, EXT warning output, DEBUG communication, UI display unit, an external input ADC units with a focus on generator control system was implemented.

A Study on the Power Divider and Combiner with Variable Power Ratio (전력 분배비를 변화시킬 수 있는 전력 분배기/합성기 구현에 관한 연구)

  • Kim, Ki-Tae;Ahn, Dal;Chung, Y.
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.347-351
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    • 2003
  • 본 논문에서는 전력 분배비를 변화시킬 수 있는 전력 분배기/합성기를 설계하였다. 전력 분배기/합성기의 ${\lambda}/4$ 전송선로 특성 임피던스를 결합선로 또는 하이브리드로 변환하여 설계하였다. 결합 선로나 하이브리드의 결합포트와 격리포트를 동시에 On/Off시킴으로써 변화하는 임피던스를 이용하여 전력 분배비가 1:1에서 1:0으로 즉 전력이 두개의 포트에 같은 크기로 전달되다가 모든 입력이 하나의 출력포트로 모두 전달되는 전력 분배기를 설계하였다.

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