• The Journal of the Acoustical Society of Korea
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• v.11 no.6
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• pp.15-22
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• 1992

i.i.d 신호의고차 모멘트와 스펙트럼의 성질에 대하여 4차까지 고찰하였으며 이의 결과를 이용하 여 2차 Volterra 급수로 표시되고, i.i.d. 입력 신호를 갖는 시불변 비선형 시스테므이 파라메타들을 추정 하는 알고리즘을 시간 영역과 주파수 영역에서 각각 제안하였다. 비록 2차 Volterra 급수가 i.i.d. 입력 신호에 대하여 orthogonal 모델이 아닐지라도 입력 신호의 각종 시간지연에 대한 모멘트나 역행렬의 계 산등이 요구되지 않으며 선형 전달함수와 2차 전달함수를 추정할 수 있는 알고리즘이 존재하는 것을 보 았다.

• The KIPS Transactions:PartB
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• v.8B no.6
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• pp.699-704
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• 2001

ABSTRACT In this paper, a new hybrid modular recurrent TDNN (time-delay neural network)-HMM (hidden Markov model) architecture for speech recognition has been studied. In TDNN, the recognition rate could be increased if the signal window is extended. To obtain this effect in the neural network, a high-level memory generated through a feedback within the first hidden layer of the neural network unit has been used. To increase the ability to deal with the temporal structure of phonemic features, the input layer of the network has been divided into multiple states in time sequence and has feature detector for each states. To expand the network from small recognition task to the full speech recognition system, modular construction method has been also used. Furthermore, the neural network and HMM are integrated by feeding output vectors from the neural network to HMM, and a new parameter smoothing method which can be applied to this hybrid system has been suggested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.17-22
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• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.

• Convergence Security Journal
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• v.6 no.1
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• pp.55-63
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• 2006

In this paper, an algorithm that provisions absolute differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features an adaptive scheme that compensates the deviation for prediction on the traffic to be arrived continuously. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot, and derives the deviation between the two quantity. The deviation is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the constant rate traffic. It is demonstrated through simulation that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional mechanism.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3986-3994
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• 2000

A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] $\bigodot$,$\square$ [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction($\bigodot$). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction($\bigodot$) could be generated nearly in the almost same condensed time as the input components are fel>ded in the dyadic pipeline unitlo) or the output components are drained out of the dyadic pipeline unit($\square$), so called a dedicated chained pipeline unit for only a inner product operation.

• Journal of IKEEE
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• v.27 no.3
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• pp.234-238
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• 2023

In this paper, we propose a time-to-digital converter (TDC) with compensation capability for PVT (process, voltage, and temperature) variations. A typical delay line-based TDC measures time based on the inverter's propagation delay, making it fundamentally sensitive to PVT variations. This paper presents a method to minimize the resolution change of TDC by compensating for the propagation delay caused by the PVT variations. Additionally, it dopts Cyclic Vernier TDC (CVTDC) structure to provide a wide input detection range. The proposed CVTDC with PVT compensation function is designed using a 45nm CMOS process, consumes 8mW of power, offers a TDC resolution of 5 ps, and has an input detection range of about 5.1 ns.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.265-268
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• 1998

본 논문에서는 1채널(mono)이나 2채널(stereo)의 오디오 입력을 5채널(center, left, right, left side, right side)로 출력시키는 음장 시스템을 설계하고 그 성능을 분석하였다. 가정의 리스닝 룸 같이 작은 공간에서 콘서트 홀 같은 커다란 공간의 음장을 재현하기 위한 멀티 채널 음장 시스템은 지연기, 초기 반사음처리기, 잔향기를 이용해 설계하였다. 초기 반사음 처리기의 지연과 이득은 실제 공간에서 측정한 암펄스 응답을 이용하여 결정하였으며, 구현된 초기 반사음을 전방 30$^{\circ}$방향에서 재생함으로써 확장감을 증가시킬 수 있도록 하였다. 잔향기는 자연스러운 주파수 및 감쇠 특성을 갖도록 설계되었으며, 후방 60$^{\circ}$방향에서 재생되는 잔향의 상관 계수를 작게 함으로써 청취시 공간감을 느끼게 하였다. 설계된 음장 시스템은 무향실 데이터를 입력으로 시뮬레이션되었고, 그 결과로 얻어진 5개의 PCM 출력은 멀티 트랙 재생 장치에 의해 일반 리스닝 룸에서 재생된다.

• The Journal of Information Technology
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• v.1 no.2
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• pp.65-79
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• 1998

In this thesis, a buffer alloction and management algorithm is proposed in order to satisfy the QoS of CBR/VBR traffics incomming to ATM networks. Proposed traffic menagement algorithm is based on the route seperation mechanism that allocates buffers acoording to traffic characterics, and sets threshold to allocated buffers. We developed a cell scheduling algorithm and evaluated cell delay and loss probability characteristics according to incomming traffic classes. The cell scheduling algorithm uses buffer size thresholds to control overload traffic flow.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.11-14
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• 2000

본 논문에서는 재귀적 지연추정기를 갖는 적응여파기를 이용하여 음성신호에 내재한 배경잡음을 제거하는 단일입력 적응잡음제거기를 TMS320C30 EVM 보드에서 실시간 구현하였다. 이를 위하여 샘플시간마다 지연정보를 구할 수 있는 재귀적 평균 절대차 함수를 사용하고, 정규화 된 최소평균자승(NLMS: Normalized Least Mean Square) 알고리듬을 사용하는 단일입력 잡음제거 시스템을 시뮬레이션한 (1)의 내용을 EVM 보드에 구현하였다. 그리고, (1)과 동일한 방법으로 백색 가우시안 잡음에 의해 왜곡된 음성에 대하여 SNR(Signal-to-Noise Ratio)에 따른 잡음제거 실험을 하였으며, EVM 보드에서의 실험결과를 (1)의 시뮬레이션 결과와 비교/검토하였다.