• Journal of the Korean Society for Precision Engineering
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• v.32 no.10
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• pp.897-902
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• 2015

This study reports on a uniform resin coating method by using a doctor blade type dispenser. For high productivity, continuous imprint-lithography has been studied, and developed fabrication systems are used in several applications such as anti-reflection films, dry adhesives, and water collecting surfaces. In the continuous fabrication field, researchers have typically focused on patterning and demolding procedures. During the roll-to-roll fabrication process, however, the uniform resin coating process is also important in order to obtain a high quality product, which can be evaluated by uniform thickness, precise geometric expressions, and a thin residual layer. To achieve these, a doctor blade type dispenser was designed and fabricated. As a result, thickness of coated resin was well controlled by modulating the flow rate of the resin and blading gap. In addition, a very thin layer coating process (${\sim}10{\mu}m$) was achieved by softly contacting the blade on the substrate.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.12
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• pp.1419-1424
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• 2011

Nanoimprint lithography is a next generation lithography technology, which enables to fabricate nano to micron-scale patterns through simple and low cost process. Nanoimprint lithography has been applied in various industry fields such as light emitting diodes, solar cells and display. Functional patterns, including anti-reflection moth-eye pattern, photonic crystal pattern, fabricated by nanoimprint lithography are used to improve overall efficiency of devices in that fields. For these reasons, in this study, sub-micron-scaled functional patterns were directly fabricated on Si and glass substrates by thermal imprinting process using ZnO nano-particles dispersion resin. Through the thermal imprinting process, arrays of sub-micron-scaled pillar and hole patterns were successfully fabricated on the Si and glass substrates. And then, the topography, components and optical property of the imprinted ZnO nano-particles/resin patterns are characterized by Scanning Electron Microscope, Energy-dispersive X-ray spectroscopy and UV-vis spectrometer, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.1
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• pp.114-120
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• 2012

We present a simple and low-cost method to fabricate poly(methyl-methacrylate) (PMMA) nanochannels with various shapes by combining the standard optical lithography with a PMMA layer transfer and collapse technique. We utilized PMMA membrane reflowing/collapsing phenomena into microchannels to fabricate nanochannels at both corners of arbitrarily-shaped microchannels. This allows nanochannels with various shapes such as curved nanochannels as well as straight nanochannels to be easily fabricated since the shape of the microchannel determines the shape of the nanochannels. This nanochannel fabrication method is simple, flexible, and low-cost since the standard optical lithography with low-resolution optical masks can be used to fabricate nanoscale channels as small as 100 nm wide with various shapes. Also, the sealing of nanochannels can be naturally achieved while the nanochannels are formed through the polymer layer transfer and collapse.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.63.1-63.1
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• 2011

현재 상용 중인 터치패널의 전도성 필름으로는 ITO가 주로 사용된다. 하지만, 디스플레이 기기의 수요 증가와 Indium의 고갈로 인한 ITO의 수요 공급 불균형으로 인한 원가 문제가 대두되고 있다. 이 때문에, Carbon nanotube (CNT), Graphene 등의 대체 투명 전도성 물질들이 연구 중에 있지만 투과율 및 저항 문제 등이 문제가 되고 있다. 본 연구에서는 투명 전도성 필름의 광 투과도 향상을 위하여, 자외선 경화 레진을 이용하여, 전도성 필름 상에 모스 아이 레진 패턴을 형성하는 실험을 진행하였다. 패턴이 형성된 이후에는 Scanning Electro Microscope를 통하여 패턴의 형성 유무를 관찰하였고, UV-vis와 4-point probe를 이용하여 투과도 및 저항을 측정하였다. 실험 결과 모스아이패턴을 필름에 패터닝 함으로써, 전체적으로 투과도가 증가된다는 것을 확인 할 수 있었으며, 투과도의 증가폭은 단면 패터닝보다는 양면 패터닝을 한 경우가 높았다. 그리고 저항 변화에 있어서는 패턴이 있는 부분의 경우 표면 잔여층으로 인하여 급격하게 증가하였지만, 전도면 반대편에 패터닝을 진행한 경우 거의 변화하지 않았다는 것을 확인할 수 있었다. 결과적으로, 본 연구를 통해 나노 임프린트 리소그래피를 통해 전도성 폴리머 필름 상부에 모스아이나노 구조물을 제작하였고, 이를 통해 기존의 전도성 폴리머 필름의 낮은 투과율을 향상시킬 수 있었다.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.2
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• pp.239-244
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• 2011

Nano Imprint Lithography(NIL) is technique for copying a pattern from stamp with nano size pattern in order to replicated the materials. It is very important to demold in order to make NIL process effectively. Self Assembled Monolayers(SAM) coater is manufactured by means of decreasing surface energy with the stamp surface treatment to improve release characteristics. Manufactured device contains tilting and rotation option for increasing process life time by coating on the sidewall of the pattern in stamp. The stamp coated with optimized tilting angle $30^{\circ}$ and rotation speed of 10rpm has more imprinting cycles than the stamping coated without tilting and rotation. Effective SAM coating on the sidewall of the pattern in stamp will improve by 50% of process life time.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.5
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• pp.420-425
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• 2008

PMMA light guiding plate with nano-sized pattern was fabricated using anodized aluminum oxide membrane as a template for nano imprint lithography. Nano-sized pore arrays were prepared by the self-organization processes of the anodic oxidation using the aluminum plate with 99.999% purity. Since the aluminum plate has a rough surface, the aluminum plate with thickness of 1mm was anodized after the pre-treatments of chemical polishing, and electrochemical polishing. The surface morphology of the alumina obtained by the first anodization process was controlled by the concentration of electrochemical solution during the first anodization. The surface morphology of the alumina was also changed according to temperature of the solution during chemical polishing performed after first anodization. The pore widening process was employed for obtaining the one-channel with flat surface and height of the channel because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. It is shown from SPM results that the nano-sized pattern on PMMA light guiding plate fabricated by nano imprint lithography method was well transferred from that of anodized aluminum oxide template.

• KSBB Journal
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• v.22 no.6
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• pp.433-437
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• 2007

A constant desire has been to fabricate nanopatterns for biochip and the Ultraviolet-nano imprint lithography (UV-NIL) is promising technology especially compared with thermal type in view of cost effectiveness. By using this method, nano-scale to micro-scale structures also called nanopore structures can be fabricated on large scale gold plate at normal conditions such as room temperature or low pressure which is not possible in thermal type lithography. One of the most important methods in fabricating biochips, immobilizing, was processed successfully by using this technology. That means immobilizing proteins only on the nanopore structures based on gold, not on hardened resin by UV is now possible by utilizing this method. So this selective nano-patterning process of protein can be useful method fabricating nanoscale protein chip.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.1838-1843
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• 2014

Nanoimprint lithography (NIL) fabrication process is regarded as the main alternative to existing expensive photo-lithography in areas such as micro- and nano-electronics including optical components and sensors, as well as the solar cell and display device industries. Functional patterns, including anti-reflective moth-eye pattern, photonic crystal pattern, fabricated by NIL can improve the overall efficiency of such devices. To successfully imprint a nano-sized pattern, the process conditions such as temperature, pressure, and time should be appropriately selected. In this paper, a cavity-filling process of the moth-eye pattern during the thermal-NIL within the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer, were investigated with three-dimensional finite element analysis. The effects of initial thickness of polymer resist and imprinting pressure on cavity-filling process has been discussed. From the analysis results it was found that the cavity filling can be completed within 100 s, under the pressure of more than 4 MPa.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.25-29
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• 2014

In this study, an optical PCB was proposed which can overcome the limitations of the conventional PCB, and a new structure with pluggable lens was considered for a high-efficient passive alignment. The structure was a lens-added optical waveguide for the improvement of misalignment between the lens and the waveguide in the alignment. Also, as it had a barrier-type structure to prevent the surface damage of the lens by desorption, the high-efficient passive alignment can be realized. The structure was designed by optimizing the simulation and the fabrication process of the pluggable lens structure was conducted using the repetitive photolithography and the thermal reflow. The optical waveguide with the lens-integrated pluggable interconnection was fabricated by the imprint process using the polydimethylsiloxane(PDMS) replica mold. Therefore, we confirmed the possibility of pluggable lens-added optical waveguide structure fabrication for high-efficient passive alignment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.