• Title/Summary/Keyword: 임계출력

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Real-Time Step Count Detection Algorithm Using a Tri-Axial Accelerometer (3축 가속도 센서를 이용한 실시간 걸음 수 검출 알고리즘)

  • Kim, Yun-Kyung;Kim, Sung-Mok;Lho, Hyung-Suk;Cho, We-Duke
    • Journal of Internet Computing and Services
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    • v.12 no.3
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    • pp.17-26
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    • 2011
  • We have developed a wearable device that can convert sensor data into real-time step counts. Sensor data on gait were acquired using a triaxial accelerometer. A test was performed according to a test protocol for different walking speeds, e.g., slow walking, walking, fast walking, slow running, running, and fast running. Each test was carried out for 36 min on a treadmill with the participant wearing an Actical device, and the device developed in this study. The signal vector magnitude (SVM) was used to process the X, Y, and Z values output by the triaxial accelerometer into one representative value. In addition, for accurate step-count detection, we used three algorithms: an heuristic algorithm (HA), the adaptive threshold algorithm (ATA), and the adaptive locking period algorithm (ALPA). The recognition rate of our algorithm was 97.34% better than that of the Actical device(91.74%) by 5.6%.

Design of a Low Power Turbo Decoder by Reducing Decoding Iterations (반복 복호수 감소에 의한 저전력 터보 복호기의 설계)

  • Back, Seo-Young;Kim, Sik;Back, Seo-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.1C
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    • pp.1-8
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    • 2004
  • This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

A Continuous Conduction mode/Critical Conduction Mode Active Power Factor Correction Circuit with Input Voltage Sensor-less Control (입력전압을 감지하지 않는 전류연속/임계동작모드 Active Power Factor Correction Circuit)

  • Roh, Yong-Seong;Yoo, Changsik
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.151-161
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    • 2013
  • An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

Prediction of Thermal-Hydraulic Phenomena in the LBLOCA Experiment L2-3 Using RELAP5/MOD2 (RELAP5/MOD2 코드에 의한 대형냉각재 상실사고 모사실험 L2-3의 열수력 현상 예측)

  • Bang, Young-Seok;Chung, Bub-Dong;Kim, Hho-Jung
    • Nuclear Engineering and Technology
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    • v.23 no.1
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    • pp.56-65
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    • 1991
  • The LOFT LOCE L2-3 was simulated using the RELAP5/MOD2 Cycle 36.04 code to assess its capability in predicting the thermal-hydraulic phenomena in LBLOCA of a PWR. The reactor vessel was simulated with two core channels and split downcomer modeling for a base case calculation using the frozen code. The result of the base calculation showed that the code predicted the hydraulic behavior, and the blowdown thermal response at high power region of the core reasonably and that the code had deficiencies in the critical How model during subcooled-two-phase transition period, in the CHF correlation at high mass flux and in the blowdown rewet criteria. An overprediction of coolant inventory due to the deficiencies yielded the poor prediction of reflood thermal response. Improvement of the code, RELAP5 / MOD2 Cycle 36.04, based on the sensitivity study increased the accuracy of the prediction of the rewet phenomena.

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New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm (Radix-2 MBA 기반 병렬 MAC의 VLSI 구조)

  • Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.94-104
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    • 2008
  • In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

Flaw Detection of Ultrasonic NDT in Heat Treated Environment Using WLMS Adaptive Filter (열처리 환경에서 웨이브렛 적응 필터를 이용한 초음파 비파괴 검사의 결함 검출)

  • 임내묵;전창익;김성환
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.7
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    • pp.45-55
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    • 1999
  • In this paper, we used the WLMS(Wavelet domain Least Mean Square) adaptive filter based on the wavelet transform to cancel grain noise. Usually, grain noise occurs in changes of the crystalline structure of metals in high temperature environment. It makes the detection of flaw difficult. The WLMS adaptive filtering algorithm establishes the faster convergence rate by orthogonalizaing the input vector of adaptive filter as compared with that of LMS adaptive filtering algorithm in time domain. We implemented the WLMS adaptive filter by using the delayed version of the primary input vector as the reference input vector and then implemented the CA-CFAR(Cell Averaging- Constant False Alarm Rate) threshold estimator. CA-CFAR threshold estimator enables to detect the flaw and back echo signals automatically. Here, we used the output signals of adaptive filter as its input signal. To Cow the statistical characteristic of ultrasonic signals corrupted by grain noise, we performed run test. The results showed that ultrasonic signals are nonstationary signal, that is, signals whose statistical properties vary with time. The performance of each filter is appreciated by the signal-to-noise ratio. After LMS adaptive filtering in time domain, SNR improves to about 2-3㏈ but after WLMS adaptive filtering in wavelet domain, SNR improves to about 4-6㏈.

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The Operating Characteristics of DBR-LD with Wavegudies Coupling Structure (도파로 결합 구조에 따른 DBR-LD의 동작특성)

  • 오수환;박문호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.666-672
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    • 2003
  • In this paper, we described the fabrication and the performance of wavelength tunable distributed bragg reflector (DBR) laser diode (LD), having different waveguide coupling mechanisms; integrated-twin-guide (ITG) DBR-LD and butt coupled (BT) DBR-LD. This deviceis fabricated by metal organic vapor phase epitaxy (MOVPE) growth and planar buried heterostructure (PBH)-type transverse current confinement structure. The result of measurement, the optical performance of BT-DBR-LD is better over 2 times than that of ITG-DBR-LD at the variation of threshold current and output power, and slop efficiency due to the higher coupling efficiency of the butt coupled structure than the integrated twin guide structure. The maximum wavelength tuning range is about 7.2nm for ITG DBR-LD and 7.4nm for BT DBR-LD. Both types of lasers have a very high yield of single mode operation with a side-mode suppression ratio of more than 35dB.

Design and Electromagnetic Characteristics of Planar Transformer (평면변압기의 설계와 전자기적 특성)

  • Kim, Hyun-Sik;Lee, Hae-Yeon;Kim, Jong-Ryung;Oh, Young-Woo
    • Journal of the Korean Magnetics Society
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    • v.12 no.3
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    • pp.109-116
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    • 2002
  • We designed the flyback planar transformer, which had 8 W capacity, with 70 V input voltage and 8.2 V output voltage for the establishment of design method and the confirmation of application possibility. The numerical value of inductance measured under the switching frequency of 120 kHz was 1650 $\mu$H, which was the inductance efficiency of'85∼87% against theoretical value. The A.C. resistance of primary and secondary coil was 4.2 Ω and 0.25 Ω respectively, On the other hand, the quality factor for each wound numbers showed quite a high value of 158 and 75 respectively. And the Coupling Factor was 0.96∼0.97 under 120 kHz switching frequency. The inductance rapidly increased as the thickness of the core plane increased until it became 1.4 mm but under the thickness more than 1.4 mm, there was no substantial change. Therefore, the critical value of the plane thickness of core was 1.4 mm. And the shape of the output wave of the planar transformer at 70V input voltage was a stable square wave.

ITO, PR, 격벽 재료의 레이저 직접 미세가공

  • Lee, Cheon;Lee, Gyung-Chul;Ahn, Min-Young;Lee, Hong-Gyu
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.80-80
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    • 1999
  • 플라즈마 디스플레이 패널(PDP)의 공정을 간단히 하기 위하여 포토레지스트, ITO, 격벽재료를 Ar+ laser(λ-514 nm, CW)와 Nd:YAG laser(λ=532, 266nm, pulse)로 직접 패터닝 하였다. 레이저에 의한 포토레지스트의 패턴결과, 아르곤 이온 레이저의 포토레지스트 가공의 반응 메카니즘은 레이저 빔의 열에 의한 시료 표면의 국부적인 온도상승에 의한 용융작용이며, 그 결과 식각 후 형성된 패턴의 단면 모양도 레이저빔의 profile과 같은 가우시안 형태를 나타낸다. Nd:YAG 레이저의 4고조파(532nm)를 이용한 경우 200$\mu\textrm{m}$/sce의 주사속도에서 포토레지스트를 패턴하기 위한 임계에너지(threshold energy fluence) 값은 25J/cm2이며, 약 40J/cm2의 에너지 밀도에서 하부기판의 손상이 발생하기 시작하였다. 글미 1은 Nd:YAG 레이저 4고조파를 이용하여 포토레지스트를 식각한 경우 SEM 표면사진(위)과 단차특정기에 의한 단면형상(아래)이다. ITO 막의 레이저에 의한 직접 패턴 결과, ITO 막은 레이저 펄스에 의한 급속 가열 및 증발에 의한 메커니즘으로 식각이 이루어지며, 레이저 파장에 따른 광흡수 정도의 차이에 의해 2고조파 (532nm)에서 ITO 막의 가공 품질이 4고조파(266nm)에 비해 우수하며 패턴의 폭도 출력에 따라 제어가 용이하였다. 그림 2는 Nd:YAG 레이저 2고조파를 이용하여 ITO를 식각한 경우 SEM표면 사진(위)과 단차측정기에 의한 단면형상(아래)이다. 격벽 재료의 레이저에 의한 직접 패턴 결과, Ar+ 레이저(514nm)는 출력 밀도 32NW/cm2에서 격벽을 유리 기판의 경계면까지 식각하였다. Nd:YAG 레이저(532nm)는 laser fluence가 6.5mJ/cm2에서 격벽을 식각하기 시작하였으며, 19.5J/cm2에서 유리기판의 rudraus(격벽 두께 130$\mu\textrm{m}$)까지 식각하였다.

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A Study on Optimal ERP and Antenna HAAT for Transmission of the 8-VSB DTTB (8-VSB DTTB 송신을 위한 최적 ERP와 안테나 HAAT에 관한 연구)

  • 김재섭;임승우
    • Journal of the Korea Computer Industry Society
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    • v.2 no.9
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    • pp.1147-1154
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    • 2001
  • In this paper, we make plans for facilities, the 8-VSB DTV transmission system, installed in the near future, based on presently NTSC TV operating it. First of all we estimate transmission power for analog NTSC, digital 8-VSB terrestrial broadcasting and the effective condition of optimal receiving power result from it. It's also to estimate optimal receiving condition by using Longley-Rice's Field Strength calculating method that is to guess a profile between transmitting station and many receiving points. The 8-VSB DTV Propagation aims to high-speed transmission rates of 19.39Mbps datum to enable HDTV(High Definition Television) at NTSC 6MHz bandwidth. First of all, an optimization of field strength between transmission station and receiver must deal with considerable. Because of these reasons, 8-VSB DTV transmission needs effective extension for NTSC TV service coverage. Finally we present the transmitting output that is expected in changing NTSC VHF to DTV UHF for maintaining the transmitting output of NTSC TV that is equal to 8-VSB DTV in service coverage.

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