• Journal of Korean Electronics
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• v.1 no.11
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• pp.21-30
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• 1981

• Journal of Korean Electronics
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• v.2 no.7
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• pp.45-51
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• 1982

• Journal of Korean Electronics
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• v.2 no.11
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• pp.17-29
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• 1982

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.35-37
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• 2001

다층 인쇄 회로 기판에 Combline 구조를 가진 스트립 라인 또는 마이크로 스트립 라인 대역통과 필터를 구현하였다. 저 비용 구현과 이동성과 휴대성을 강조하기 위해 기존의 세라믹 대신 FR4 와 에폭시를 기반으로 하는 다층 회로 기판의 도체 층에 집적화하였다. Combline 각 끝단에 커패시터를 부하 함으로써 전기적 길이를 화장하였고 전체적인 크기를 감소시킴으로서 적당한 필터 특성을 얻을 수 있었다. 구현된 필터는 마이크로파 대역에서 사용 가능하며 특히 Bluetooth나 Wireless LAN 과 같은 ISM 대역을 사용하는 무선통신소자로서 사용 가능하다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.2
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• pp.245-253
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• 2010

The reliability problems of flip chip packages subjected to temperature change during the packaging process mainly occur due to mismatches in the coefficients of thermal expansion as well as features with time-dependent material properties. Resin molding compounds like glass fiber reinforced epoxy composites used as the dielectric layer in printed circuit boards (PCB) strongly exhibit viscoelastic behavior, which causes their Young's moduli to not only be temperature-dependent but also time-dependent. In this study, the stress relaxation and creep tests were used to characterize the viscoelastic properties of the glass fiber reinforced epoxy composite. Using the viscoelastic properties, finite element analysis (FEA) was employed to simulate thermal loading in the pre-baking process and predict thermal warpage. Furthermore, the effect of viscoelastic features for the major polymeric material on the dielectric layer in the PCB (the glass fiber reinforced epoxy composite) was investigated using FEA.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.11
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• pp.23-31
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• 2003

• Annual Conference on Human and Language Technology
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• 1991.10a
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• pp.287-299
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• 1991

본 논문은 하드웨어 구현이 가능한 신경 회로망을 구성하여 한글 문자 인식을 수행하였다. 먼저 입력 장치로부터 받아들인 문자 영상은 인식 속도를 높히기 위하여 특별한 전처리 과정 없이 직접 피쳐를 추출하였으며 추출한 피쳐로는 하드웨어 구현이 용이한 교차 피쳐와 투영 피쳐를 이진화로 코딩하였다. 신경 회로망의 하드웨어 구현을 가능하게 하기위해서 정수형 연결 강도와 비선형 Hard-limit 함수를 가지고 학습을 하는 Rounding 학습 방법을 도입하여 학습시켰으며 한글의 구조적 특성을 이용하여 한글을 유형별로 Module화 및 Submodule화 작업을 수행한 다음 인식하는 계층적인 문자 인식 시스템을 구성하였다. 그리고 이러한 방법을 이용하여 한글 문자 인식용 CMOS 신경회로망 Chip을 설계하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.465-472
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• 2016

This study materialized an FPGA-based system to extract PCB patterns. The Printed Circuit Boards that are produced these days are becoming more detailed and complex. Therefore, the importance of a vision system to extract defects of detailed patterns is increasing. This study produced an FPGA-based system that has high speed handling for vision automation of the PCB production process. A vision library that is used to extract defect patterns was also materialized in IPs to optimize the system. The IPs materialized are Camera Link IP, pattern matching IP, VGA IP, edge extraction IP, and memory IP.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.3 s.180
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• pp.102-109
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• 2006

Several methods for PCB pattern inspection have been tried to detect fine detects in pad contours, but their low detection accuracy results from pattern variations originating from etching, printing and handling processes. The adaptive inspection algorithm has been newly proposed to extract minute defects based on movable segments. With gerber master images of PCB, vertex extractions of a pad boundary are made and then a lot of segments are constructed in master data. The pad boundary is composed of segment units. The proposed method moves these segments to optimal directions of a pad boundary and so adaptively matches segments to pad contours of inspected images, irrespectively of various pattern variations. It makes a fast, accurate and reliable inspection of PCB patterns. Its performances are also evaluated with several images.