• Title/Summary/Keyword: 인덕턴스 특성

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Fabrication and characterization of the 0.25 ${\mu}m$ T-shaped gate P-HEMT and its application for MMIC low noise amplifier (0.25 ${\mu}m$ T형 게이트 P-HEMT 제작 및 특성 평가와 MMIC 저잡음 증폭기에 응용)

  • Kim, Byung-Gyu;Kim, Young-Jin;Jeong, Yoon-Ha
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.1
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    • pp.38-46
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    • 1999
  • o.25${\mu}m$ T-shaped gate P-HEMT is fabricated and used for design of X0band three stage monolithic microwave integrated circuit(MMIC) low noise amplifier(LNA). The fabricated P-HEMT exhibits an extrinsis transconductance of 400mS/mm and a drain current of 400mA/mm. The RF and noise characteristics show that the current gain cut off frequency is 65GHz and minimum noise figure(NFmin) of 0.7dB with an associated gain of 14.8dB at 9GHz. In the design of the three stage LNA, we have used the inductive series feedback circuit topology with the short stub. The effects of series feedback to the noise figure, the gain, and the stability have been investigated to find the optimal short stub length. The designed three staage LNA showed a gain of above 33dB, a noise figure of under 1.2dB, and ainput/output return loss of under 15dB and 14dB, respectively. The results show that the fabricated P-HEMT is very suitable for a X-band LNA with high gain.

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Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process (pHEMT 공정을 이용한 저손실, 고전력 4중 대역용 SP6T 스위치 칩의 설계 및 제작)

  • Kwon, Tae-Min;Park, Yong-Min;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.584-597
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    • 2011
  • In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

Magnetic Properties of Chip Inductors Prepared with V2O5-doped Ferrite Pastes (V2O5 도핑한 페라이트 페이스트로 제조된 칩인덕터의 자기적 특성)

  • Je, Hae-June
    • Journal of the Korean Magnetics Society
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    • v.13 no.3
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    • pp.109-114
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    • 2003
  • The purpose of this study Is to investigate the effect of $V_2$O$_{5}$ addition on the microstructures and magnetic properties of 7.7${\times}$4.5${\times}$1.0 mm sized multi-layer chip inductors prepared by the screen printing method using 0∼0.5 wt% $V_2O_{5}$-doped NiCuZn ferrite pastes. With increasing the $V_2O_{5}$ content, the exaggerated grain growth of ferrite layers was developed due to the promotion of Ag diffusion and Cu segregation into the grain boundaries oi ferrites, which affected significantly the magnetic properties of the chip inductors. After sintering at $900^{\circ}C$, the inductance at 10 MHZ of the 0.5 wt% $V_2O_{5}$-doped chip inductor was 3.7 ${\mu}$H less than 4.2 ${\mu}$H of the 0.3 wt% $V_2O_{5}$-doped one, which was thought to be caused by the residual stress at the ferrite layers increased with the promotion of Ag diffusion and Cu segregation. The quality factor of the 0.5 wt% $V_2O_{5}$-doped chip inductor decreased with increasing the sintering temperature, which was considered to be caused by the electrical resistivity of the ferrite layer decreased with the promotion of Ag/cu segregation at the grain boundaries and the growth of the mean grain size of ferrite due to exaggerated grain growth of ferrite layers.

Stacked Pad Area Away Package Modules for a Radio Frequency Transceiver Circuit (RF 송수신 회로의 적층형 PAA 패키지 모듈)

  • Jee, Yong;Nam, Sang-Woo;Hong, Seok-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.10
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    • pp.687-698
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    • 2001
  • This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

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Development of Tacho Generator for Application of Anti-aircraft Weapon System (대공무기체계 적용을 위한 타코제너레이터 개발)

  • Byun, Kisik;Park, Jun Young;Cho, Sung-Yong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.10
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    • pp.174-180
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    • 2020
  • This paper presents the development of a tacho generator that is applicable to a DC motor for anti-aircraft weapon systems. In general, devices such as tacho generators and resolvers are used as feedback devices for controlling DC motors. A tacho generator with a wide operating temperature range was developed, which has robust characteristics against shock loads and vibrations according to the operational characteristics of anti-aircraft weapon systems. The target specifications were set based on the requirements of the tacho generator currently in operation. A rotor coupled to the shaft of the motor and a stator coupled to the housing of the motor were then designed and manufactured. The inductance was 31.0 mH, the terminal resistance was 147.7 ohms, and the rotational measurement factor was satisfactory under both normal operation and operating conditions after the maximum speed for the standard of 9.500 ± 0.475 V/krpm. In addition, the environmental suitability of the applied equipment was confirmed through the rate of change in unit temperature, and it was found that the temperature characteristics were all within 0.03 %/℃.

The Characteristics analysis of a Flux-lock Type Fault Current Limiter according to the Winding Directions for Power Grid (전력계통 적용을 위한 결선방향에 따른 자속구속형 한류기의 특성 분석)

  • Lee, Mi-Yong;Park, Jeong-Min
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.11
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    • pp.5879-5884
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    • 2013
  • With the rapid industrialization and economical development, the electricity demands of the industrial facilities and densely populated large cities are continuing to increase in Korea. The increase in the power consumption requires the extension of power facilities, but it is difficult to secure spaces for equipment installation in the limited space of urban areas. In addition, the 154 kV or 345 kV transmission systems in Korea has a short transmission distance, and are connected to one another in network structures that ensure the high reliability and stability of power supply. This structure reduces the impedance during the fault in power system, and increases the magnitude of in the short circuit fault current. The superconducting fault current limiter (SFCL) was devised to effectively address these existing problems. The SFCL is a new-concept eco-friendly protective device that ensures fast operation and recovery time for the fault current and does not need additional fault detection devices. Therefore, many studies are being conducted around the world. In this paper, based on the wiring method the initial fault current characteristics, current limiting characteristics, according to the incident angle and the change in inductance current limiting characteristics were analyzed in a multifaceted methods.

Characteristics of the Flux-lock Type Superconducting Fault Current Limiter According to the Iron Core Conditions (자속구속형 초전도 전류제한기의 철심조건에 따른 특성)

  • Nam, Gueng-Hyun;Lee, Na-Young;Choi, Hyo-Sang;Cho, Guem-Bae
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.7
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    • pp.38-45
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    • 2006
  • The superconducting fault current limiters(SFCLs) provide the effect such as enhancement in power system reliability due to limiting the fault current within a few miliseconds. Among various SFCLs we have developed a flux-lock type SFCL and exploited a special design to effectively reduce the fault current according to properly adjustable magnetic field after the short-circuit test. This SFCL consists of two copper coils wound in parallel on the same iron core and a component using the YBCO thin film connected in series to the secondary copper coil. Meanwhile, operating characteristics can be controlled by adjusting the inductances and the winding directions of the coils. To analyze the operational characteristics, we compared closed-loop with open-loop iron core. When the applied voltage was 200[Vrms] in the additive polarity winding, the peak values of the line current the increased up to 30.71[A] in the closed-loop and 32.01[A] in the open-loop iron core, respectively. On the other hand, in the voltages generated at current limiting elements were 220.14[V] in the closed-loop and 142.73[V] in the opal-loop iron core during first-half cycle after fault instant under the same conditions. We confirmed that the open-loop iron core had lower power burden than in the closed-loop iron core. Consequently, we found that the structure of iron core enabled the flux-lock type SFCL at power system to have the flexibility.

A Study on the Design and Fabrication of GHz Magnetic Thin Film Inductor Utilizing Co90Fe10/SiO2 Multilayer (Co90Fe10/SiO2 Multilayer를 이용한 GHz 자성박막 인덕터 설계 및 제작에 관한 연구)

  • 공기준;윤의중;진현준;박노경;문대철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.5B
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    • pp.985-991
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    • 2000
  • In this paper, the optimum structure of 2GHz magnetic thin film planar inductor were designed and fabricated to reduce the inductor area and to maximize the inductance L and quality factor Q of the inductor. The optimum design was performed utilizing Co90Fe10 layer multilayered with SiO2 layers to avoid the eddy-current skin effect and considering new lumped element model. New magnetic thin film inductors operating at 2GHz were fabricated on a Si substrate utilizing photo-lithography and lift-off techniques. The frequency characteristics of L, Q, and impedance in more than fifty identical inductors were measured using an RF Impedance Analyzer(HP4291B with HP16193A test fixture). The self-resonant frequencies(SRF) of the inductors were measured by a Vector Network Analyzer(HP8510). The developed inductors have SRF of 1.8 to 2.3GHz, L of 47 to 68nH, and Q of 70 to 80 near 1GHz. Finally, high frequency, high performance, planar micro-inductor(area=30.8 x 30.8il$^2$) with maximized L and Q were fabricated succefully.

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Design of a Low Power Capacitor Cross-Coupled Common-Gate Low Noise Amplifier (캐패시터 크로스 커플링 방법을 이용한 5.2 GHz 대역에서의 저전력 저잡음 증폭기 설계)

  • Shim, Jae-Min;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.3
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    • pp.361-366
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    • 2012
  • This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

A Small Antenna of High Radiation Efficiency Employing a Ground Radiator (그라운드 방사체를 활용한 고효율의 소형 안테나)

  • Choi, Hyeng-Cheul;Lee, Hyung-Jin;Park, Bum-Ki;Jang, Jin-Hyuk;Kim, Hyeong-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.2
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    • pp.135-143
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    • 2012
  • This paper introduces the method to utilize a terminal ground as a radiator only using reactive components without an antenna structure. Characteristics of the proposed antenna is compared with that of the meander IFA on the same ground plane($40{\times}20mm^2$) for the bluetooth band. From simulation and measurement data, it is found that the proposed antenna using only capacitors provides the highest radiation efficiency. This is because of that the higher inductance reduces radiation resistance of a ground and the capacitor has a lower loss resistance comparing to that of the IFA or the inductor. In spite of the high radiation efficiency, the area ($5{\times}2.5mm^2$) of the proposed antenna is less than half of the area ($12{\times}2.5mm^2$) of the IFA.