• The Journal of the Acoustical Society of Korea
• /
• v.14 no.3
• /
• pp.28-36
• /
• 1995

In this paper, a double loop control model using leaky delay LMS algorithm are proposed for active noise control. The proposed double loop control model estimates the loudspeaker characteristic and the error path transfer function with on-line using only gain and acoustic time delay to reduce computation burden. The control of error signal through double loop control scheme makes the more robust cntrol system. The input signal of filter to estimate acoustic time delay is used difference between input signal of input microphone and adaptive filter output. And also, in nonstationary environments, the leaky delay LMS algorithm is employed to counteract parameter drift of delay LMS algorithm. For practical noise signal, the proposed double loop control model reduces noise level about 12.9 dB.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.8 no.6
• /
• pp.561-568
• /
• 2003

There arc two ways in the output voltage control method in PWM inverters. One Is double loop voltage control composed of inner current control loop and outer voltage control loop.'rho other is single loop voltage control method composed of voltage control loop only. It's characteristics shows lower performance in case of high output impedance than double loop voltage control. However, in case of low output impedance, it shows good control performance in all load ranges than double loop voltage control. In this paper, the rule and the gain of single loop voltage control have been developed analytically and these were verified through computer simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.819-825
• /
• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of the Korean Society of Propulsion Engineers
• /
• v.20 no.4
• /
• pp.19-25
• /
• 2016

Using a actuator to which the motor and the gear is applied to the I-PD control method and a dual-loop system to carry out precise position control. I-PD control algorithm performs an operation to reduce the overshoot in the transient response. Accordingly, the actuator obtains a precise position tracking result. Also it utilizes two sensors and dual loops. It reduces the adverse effect on the precise position control that may occur by the end play of the gear train. In this paper, we uses the actuator model applying the BLDC motor and gear in order to determine the position tracking result by the dynamic characteristic change. It was verified by the simulation results.

• Proceedings of the KIPE Conference
• /
• 2011.07a
• /
• pp.194-195
• /
• 2011

본 논문은 Bi-directional Inverter(BDI)에 DQ 변환을 적용한 소신호 등가 모델과 이중 루프 제어기 설계에 대해 제안한다. 일반적으로 외부루프의 경우 동적 특성이 매우 느리기 때문에 외부루프 전달함수를 고려하지 않고 설계하는 경우가 많다. 결과적으로 시스템의 안정성이나 동적 특성이 설계한 것과 다르게 나타날 수 있다. 따라서 원하는 특성을 만족하기 위해 실험적 시행착오를 거쳐 설계를 하게 된다. 본 논문에서는 정확한 소신호 등가 모델을 제시하고 제어기를 설계한다. 제안된 방식은 PSIM 시뮬레이션 및 실험을 통해 회로해석과 소신호 등가모델의 타당성 및 제어기 설계의 타당성을 증명하였다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.5 no.1
• /
• pp.1-10
• /
• 2000

본 논문에서는 무정전전원장치(UPS)에 사용되는 3상 PWM 인버터의 정전압 제어특성 향상을 위해 개선된 형태의 데드비트 제어방식을 제안하고 이의 설계를 수행한다. 일반적으로 UPS는 전압제어 루프 안에 전류제어기를 두는 형태의 이중 제어 루프 구조를 가지며, 빠른 과도응답 제어 특성을 얻기 위해 데드비트 제어기가 많이 적용되어 왔다. 그러나 전압, 전류의 이중 제어구조를 갖는 데드비트 제어기의 경우 동일한 극배치 특성으로 인해 기존의 제어 시스템은 불안정한 측면을 갖게된다. 이러한 제어특성의 개선을 위하여 분리된 극배치를 가지는 제어기구조를 제안하며, 이는 전압제어기 출력으로 1차 지수함수 응답을 사용하는 변형된 형태의 데드비트 제어기로 구성된다. 아울러 부하 변동에 따른 부하전류의 외란성분을 전향보상하기 위하여 전차원 외란 관측기를 설계하고 시뮬레이션 및 실험을 통하여 제안된 시스템의 우수성을 확인한다.

• Journal of IKEEE
• /
• v.17 no.1
• /
• pp.16-21
• /
• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.2C
• /
• pp.191-200
• /
• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of the Korean Society of Propulsion Engineers
• /
• v.22 no.5
• /
• pp.49-58
• /
• 2018

This paper introduces a research on the control method design for the subsonic intake flow of a dual-combustion ramjet engine. To design the control method, the intake flow dynamic response characteristics, based on a designated flow condition and intake geometry, are investigated, and a control method concept considering the intake flow characteristics is established. Using a dynamic simulation model of a dual-combustion ramjet, control input/output linearized models are obtained such that a control loop design based on linearized models can be accomplished. Finally, from various control loop simulations, the performance of the control method, including its control loop stability, is evaluated.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.7
• /
• pp.1552-1558
• /
• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.