• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.888-891
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2015-2020
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• 2012

The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1463-1469
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• 2012

This paper has presented the influence of scaling theory on short channel effects of double gate(DG) MOSFET in subthreshold region. In the case of conventional MOSFET, to preserve constantly output characteristics,current and switching frequency have been analyzed based on scaling theory. To analyze the results of application of scaling theory for short channel effects of DGMOSFET, the changes of threshold voltage, drain induced barrier height and subthreshold swing have been observed according to scaling factor. The analytical potential distribution of Poisson equation already verified has been used. As a result, it has been observed that threshold voltage among short channel effects is grealty changed according to scaling factor. The best scaling theory for DGMOSFET has been explained as using modified scaling theory, applying weighting factor reflected the influence of two gates when scaling theory has been applied for channel length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2000-2006
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• 2011

In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.878-881
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel thickness and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model.

• Electrical & Electronic Materials
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• v.9 no.7
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• pp.708-718
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• 1996

The microstructure and electrical properties of the nonlinear ZnO varistor with A1$_{2}$ $O_{3}$ additions is investigated. The variation of nonlinear behavior with A1$_{2}$ $O_{3}$ additions is indicated from J-E and C-V measurement to be a result of the change of the interface defects density $N_{t}$ at the grain boundaries and the donor concentration $N_{d}$ in the ZnO grains. The optimum composition which has the nonlinear coefficients of -57 was observed in the sample with 0.005wt% A1$_{2}$ $O_{3}$ additions. The conduction mechanism at the pre-breakdown region is consistent with a Schottky thermal emission process obeying a relation given by $J^{\var}$exp[-(.psi.-.betha. $E^{1}$2/)kT] and the conduction process at the breakdown region follows a Fowler-Nordheim tunneling mechanism of the form $J^{\var}$exp(-.gamma./E).

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.591-591
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• 2012

본 연구는 Transparent conducting oxide (TCO, 산화물투명전극)를 이용한 박막태양전지 효율향상에 관한 것으로, 이중의 TCO층(Double-stacked TCO layer)의 효과적인 광학 및 전기적 설계에 관한 것이다. 기존 박막 태양전지에서는 투명전극 TCO layer로서, ITO (Indium-Tin-Oxide), FTO (Fluorine- Tin-Oxide), 및 AZO(Aluminum-doped Zinc Oxide) 등을 사용해 왔다. 각 TCO layer마다 장점이 있지만 단점 또한 존재한다. ITO의 경우 높은 전기적 특성을 가지는 반면 수소 플라즈마에 취약하고 기계적 강도에 취약해 ITO 단일층만으로 박막 태양전지에 적용하는 것에 제한을 받는다. 한편, AZO의 경우 전기적 특성도 우수할 뿐만 아니라 수소 플라즈마에도 내구성이 강한 장점이 있지만, 일함수가 p형 반도체보다 낮아 Schottky junction이 되어, 높은 전위장벽이 형성된다. 이는 정공의 이동을 방해하고, 정공의 축적이 일어나서 순방향 전압을 인가할 때 많은 전류의 감소를 가져온다. 또한, AZO와 p형 반도체 사이의 높은 직렬저항으로 인해 광전압(Voc, Open circuit voltage)와 충실률 (FF, Fill factor)가 떨어진다는 단점이 있다. 본 실험에서는 ITO/AZO 2중구조의 TCO층을 적용하여 상기의 문제점을 해결하고자 한다. 이중 구조 TCO층은 Magnetron sputter system을 이용하여, 단계적으로 증착되었다. 빛이 입사하는 유리에 ITO를 제1전도층으로 증착하였는데, ITO는 입사광의 투과도와 전기전도성이 우수하다. 제2전도층으로는 AZO층을 이용하였으며, 실리콘 반도체층과 접하게 된다. AZO는 실리콘 증착시 발생하는 수소 플라즈마에 안정적이고, 물리적 강도 또한 우수한 장점이 있다. 이중 구조층위에 실리콘 광흡수층(Si absorber)을 증착하였으며, pin 구조를 가진다. 기존, 단일막 TCO층과 2중구조 TCO층을 이용하여, 실리콘 박막 태양전지를 구성하였다. 이때, ITO/AZO의 2중구조를 적용하였을 때 태양 전지 특성이 크게 향상된 결과를 얻을 수가 있었다. 특히, 전류밀도의 경우 ITO, FTO, AZO 각각 14.5 mA/cm2, 11.2 mA/cm2, 8.18 mA/cm2를 나타낸 반면 ITO/AZO 2중구조의 경우 약 17mA/cm2 로 크게 향상 되었고, 태양전지 변환 효율도 각각 7.5%, 6.9%, 4%에서 ITO/AZO 2중 구조의 경우 8.05%로 크게 향상되었다. 본 발표에서는 2중구조 TCO를 이용한 현공정에 적용 가능한 박막태양전지 효율향상 기법에 대해 논의하고자 한다.