• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.68-76
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• 1985

A charge-coupled device (CCD) area image sensor has been demonstrated with an experi-mental 16$\times$16 prototype. The prototype is a vertical frame transfer charge.coupled imager using two-phase gate electrode structures. In this device, ion-implanted barriers are used for two -phase CCD, and NMOS process has been adopted. The total imaging setup consisting of optical lens, clock generators, clock drivels, staircase signal generators, and oscilloscope is easily achieved with the aid of PROM . English alphabets are displayed on the oscilloscope screen using the total imaging set-up. We measure charge transfer inefficiency and dark current for the fabricated devices.

• Journal of Biosystems Engineering
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• v.25 no.5
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• pp.351-358
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• 2000

This study was conducted to develop a speed control system of a DC motor which drove a barley seeder mounted on a combine harvester. Barley seeder mounted on a combine has been known to reduce labor and cost of barley cultivation. However, development of the seeder has been unsuccessful because the combine, a dedicated rice and barley harvester has not enough space and proper power take-off for barley seeder. To develop a barley seeder, small powered motor speed controller was required. A proximity sensor for detecting working speed of the combine and a programmable one board microprocessor was used to develope a control system. Motor parameters and motor constant, relationship between seeding rate, motor speed, groove volumes of a tested roller, torque were measured. The proximity sensor sent a frequency signal to the microprocessor. In laboratory experiments, the excitation voltage of the motor was shown not to be proportional to the size of pulse width (duty ratio). A table transforming frequency signal, that represented for working speed to proper pulse width was developed from seeding rate experiments. However, seeding rate at low frequency signal was not proportional to the working speed. Seeding rate control proportional to the frequency signal was achieved by shifting of the frequency signal.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Particle and aerosol research
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• v.16 no.3
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• pp.65-72
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• 2020

In this study, the indoor fine dust concentration in an office of the Korea Knowledge Industry Center was measured for about 80 hours when the concentration of atmospheric PM_2.5 was very high. The effect of the operation of the air cleaner and the forced ventilation system on the indoor PM_2.5 was investigated, and the particle size distribution of the indoor and outdoor particles was analyzed. When forced ventilator and air purifiers were partially used, the indoor PM_2.5 concentrations were maintained between 27.7 ㎍/㎥ and 32.9 ㎍/㎥ when the atmospheric PM_2.5 was 127.7 ㎍/㎥ to 141.6 ㎍/㎥ during working hours. It is more effective to operate the air purifier without operating the forced ventilation system when the concentration of the PM_2.5 is high since the PM_2.5 penetrating the installed filter is continuously introduced indoor from the outside.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.586-592
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• 2018

SRMs are difficult to design using a simple mathematical model and, consequently, numerical analysis based characteristics analysis is used including drive circuits. In this process, it is necessary to analyze the trends according to the change of the design factors, however, many of the design factors affect each other. In order to shorten the design time and achieve a proper design, a modeling technique based on the design parameters is needed. For this purpose, this paper summarizes the formulas employed for shape modeling by minimizing the number of major design factors of the SRM, and proposes a methodology for SRM design using these formulas. In particular, we propose a design method for a 6/4-pole model, one which has been studied for a long time, and showed an example of a design produced by the proposed method.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.229-229
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• 1999

교류형 플라즈마 방전 표시기(AC Plasma Display Panel, AC PDP)의 구동에서의 방전 현상은 기입방전, 유지방전, 소거 방전이 있다. 이중 유지 방전은 표시장치로서의 휘도와 계조의 표현을 위한 방전으로 표시기로서의 효율을 결정하게 된다. 본 연구에서는 유지 방전 전압의 상승 시간의 변화에 따른 방전현상과 휘도, 효율의 변화를 살펴 보았다. 방전 현상에서의 가장 큰 변화는 교류형 플라즈마 방전 표시기의 방전 개시 전압과 방전 유지 전압의 변화이다. 유지 전압의 상승시간이 증가할수록 방전 개시 전압과 방전 유지 전압의 변화이다. 유지 전압의 상승 시간이 증가할수록 방전 개시 전압과 방전 유지 전압의 차(sustain margin)는 감소하여 상승 시간이 1$\mu$s/100V 이상의 영역에서는 방전 개시 전압과 방전 유지 전압이 차이가 없어지게 된다. 이는 방전 유지 전극 위의 유전체에 쌓이게 되는 벽전하(wall charge) 양의 감소에 의한 방전 약화의 영향을 보여질 수 있다. 그러나 방전 유지 전압의 형태와 전류의 시간적인 변화를 살펴보면 이러한 약한 방전은 벽전하의 감소에 의한 방전 시의 전계 감소보다는 방전 전류의 발생 시간이 방전 전압이 증가하여 최고점에 이르지 못한 시간에 위치하여 방전이 형성될 때의 전계가 강하지 못하기 때문인 것을 알 수 있다. 방전 전류를 측정한 결과에 의하면 방전 전류의 시작은 변위 전류가 흐르고 난 후부터 시작되며 그 결과 방전 전류가 최고점에 도달하는 시간은 방전 전압 상승 시간이 길어질수록 낮은 전압에서 형성되게 된다. 또한 방전 유지 전압의 상승 시간이 길어질수록 플라즈마 방전표시기의 휘도와 효율은 낮아지고 이 결과 또한 약한 전계에서의 방전에 의한 결과로 생각되어진다.플라즈마의 강도값을 입력하여 플라즈마의 radiation을 검출하고, 스퍼터링 공정중 실질적인 in-situ 정보로 이용하였다. PEM을 통하여 In/Sn의 플라즈마 강도변화를 조사하였다. 초기 In/Sn의 플라즈마 강도(intensity)는 강도를 100하여, 산소를 주입한 결과, plasma intensity가 35 줄어들었고, 이때 우수한 ITO 박막을 얻을 수 있었다. Pulsed DC power를 사용하여 아크 현상을 방지하였다. PET 상에 coating 된 ITO 박막의 표면저항과 광투과도는 4-point prove와 spectrophotometer를 이용하여 분석하였고, AES로 박막의 두께에 따른 성분비를 확인하였다. ITO 박막의 광투과도는 산소의 유량과 sputter 된 In/Sn ion의 plasma emission peak에 따라 72%-92%까지 변화하였으며, 저항은 37$\Omega$/$\square$ 이상을 나타내었다. 박막의 Sn/In atomic ratio는 0.12, O/In의 비율은 In2O3의 화학양론적 비율인 1.5보다 작은 1.3을 나타내었다.로 보인다.하면 수평축과 수직축의 분산 장벽의 비에 따라 cluster의 두께비가 달라지는 성장을 볼 수 있었고, 한 축 방향으로의 팔 넓이는 fcc(100) 표면의 경우 동일한 Ed+Ep값에 대응하는 팔 넓이와 거의 동일한 결과가 나타나는 것을 볼 수 있다. 따라서 이러한 비대칭적인 모양을 가지는 성장의 경우도 cluster 밀도, cluster 모양, cluster의 양 축 방향 길이 비, 양 축 방향의 평균 팔 넓이로부터 각 축 방향의 분산 장벽을 얻어낼 수 있을 것으로 보인다. 기대할 수 있는 여러 장점들을 보고하고자 한다.성이 우수한 시

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1491-1496
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• 2009

This paper presents an digital based input/output interface circuit for controlling and monitoring the Diesel Engine Generator for emergency. In order to monitor and control of the Emergency Diesel Engine Generator, controlling and monitoring circuits need 5 analog input channels, 2 pick-up coil measuring circuits, 10 digital input channels containing Broken Wire Detect function, and 7 relay control signal output channels. This system performs signal processing of input signal taking advantage of simple filter circuit, photo-coupler and comparator circuit at analog input parts, and output signals for main relay is designed acting by double control, so it prevents malfunction completely. And it improves accuracy of speed input signal by applying digital circuit that processes rick-up coil signal.