• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.6
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• pp.637-645
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• 2014

This paper presents a new $4{\times}4$ multi-port amplifier(MPA) structure using reconfigurable switching matrices as input and output hybrid matrices(IHM, OHM), and phase/amplitude error calibration circuits. According to the mode selection of the switches, output power can be flexibly and effectively managed since the number of PA's to be used and the number of output port to distribute/combine amplified signals can be controlled. In addition, the proposed structure contains the phase and amplitude error calibration block that helps produce identical amplitudes and desired phase differences to the $4{\times}4$ OHM, resulting in optimizing the port-to-port isolation of the MPA system.

• 전자공학회논문지 IE
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• v.43 no.1
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• pp.16-24
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• 2006

This paper is aimed to develope of an integrated BCI(Brain Computer Interface System) that make possible for simultaneous multichannel data process and used extra cellular neural activity from the vestibular system instead of electroencephalogram signals for more precision control. The electrical properties pre-amplifier are 47.6 dB of gain, 0.005 % of distortion at 100 Hz, 12M$\Omega$ of input impedance. Window discriminator used two CPU with difference role to increase processing speed so that sampling frequency was 87 kHz. The designed window discriminator has more not only two times in signal resolution power but also ten times in error discrimination power than commericially available discriminator. The proposed method decreases 100 times in amount of integrated data then BCI system during 100 ms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of Advanced Navigation Technology
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• v.12 no.6
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• pp.604-610
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• 2008

A 2.4 GHz CMOS RF front-end using for ZigBee application is described The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF front-end is implemented in 0.18 ${\mu}m$IP6M CMOS process. The measured performance is 4.44 dB NF and -6.5 dBm IIP3 while consuming 3.28 mA current from a 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.47-55
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• 2012

A discrete-time(DT) filter with high-order temporal moving average(TMA) using actively-weighted charge sampling is proposed in this paper. To obtain different weight of sampled charge, the variable transconductance OTA is used prior to charge sampler, and the ratio of charge can be effectively weighted by switching the control transistors in the OTA. As a result, high-order TMA operation can be possible by actively-weighted charge sampling. In addition, the transconductance generated by the OTA is relatively accurate and stable by using the size ratio of the control transistors. The high-order TMA filter has small size, increased voltage gain, and low parasitic effects due to the small amount of switches and sampling capacitors. It is implemented in the TSMC $0.18-{\mu}m$ CMOS process by TMA-$2^2$. The simulated voltage gain is about 16.7 dB, and P1dB and IIP3 are -32.5 dBm and -23.7 dBm, respectively. DC current consumption is about 9.7 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

• Journal of Biomedical Engineering Research
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• v.25 no.5
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• pp.343-349
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• 2004

Electroglottograph(EGG) is a signal recorded from the vocal cord vibration by measuring electrical impedance across the vocal folds through the neck skin. The purpose of this study was to develop EGG system and to evaluate possibility for the application on speech analysis and laryngeal disease diagnosis. EGG system was composed of two pairs of ring electrodes, tuned amplifier, phase sensitive detector, low pass filter, and auto-gain controller. It was designed to extract electric impedance after detecting by amplitude modulation method with 2.7MHz carrier signal. Extracted signals were transmitted through line-in of PC sound card, sampled and quantized. Closed Quotient(CQ), Speed Quotient(SQ), Speed Index(SI), fundamental frequency of vocal cord vibration(F0), pitch variability of vocal fold vibration (Jitter), and peak-to-peak amplitude variability of vocal fold vibration(Shimmer) were analyzed as EGG parameters. Experimental results were as follows: the faster vocal fold vibration, the higher values in CQ parameter and the lower values in SQ and SI parameters. EGG and speech signals had the same fundamental frequency. CQ, SQ, and SI were significantly different between normal subjects and patients with laryngeal cancer. These results suggest that it is possible to implement portable EGG system to monitor the function of vocal cord and to test functional changes of the glottis.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.