• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.27-34
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• 2003

Recently, an efficient hardware development for a cryptosystem is concerned. The efficiency of a multiplier for GF($2^n$)is directly related to the efficiency of some cryptosystem. This paper, considering the trade-off between time complexity andsize complexity, proposes a new multiplier architecture having n[n/2] AND gates and n([n/2]+1)- $$\Delta$_n$ = XOR gates, where $$\Delta$_n$=1 if n is even, $$\Delta$_n$=0 otherwise. This size complexity is less than that of existing ${multipliers}^{[5][12]}$which are $n^2$ AND gates and $n^2$-1 XOR gates. While a new multiplier is a serial-parallel multiplier to output a result of multiplication of two elements of GF($2^n$) after 2 clock cycles, the suggested multiplier is more suitable for some cryptographic device having space limitations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.511-514
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• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.880-883
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• 2005

This paper presents a method of constructing the sequential logic machines over finite fields(or galois fields). The proposed the sequential logic machines is constructed by as following. First of all, we obtain the linear characteristics between present state and next state based on mathematical properties of finite fields and sequential logic machines. Next, we realize the sequential logic machines over finite field GF(P) using above linear characteristics and characteristic polynomial that expressed using by matrix.

• Review of KIISC
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• v.1 no.3
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• pp.30-34
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• 1991

유한체의 이사로그 문제는pne-way 함수의 특성을 잘 나타내고 있어, 암호 시스템 에 많이 응용되고 있다. 본 논문에서는 기존의 이산로그와 관련된 알고리즘들을 분석 약술 하고 그중 가장 효율적인 알고리즘으로 평가되는 Coppersmity알고리즘을 4GF({2^127})$ 에서 구현한 결과를 일부분 공개한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.628-636
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• 2010

In this paper, we present a new type high speed parallel multiplier for performing the multiplication of two polynomials using standard basis in the finite fields GF($2^m$). Prior to construct the multiplier circuits, we design the basic cell of vector code generator(VCG) to perform the parallel multiplication of a multiplicand polynomial with a irreducible polynomial and design the partial product result cell(PPC) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial with VCG circuits. The presented multiplier performs high speed parallel multiplication to connect PPC with VCG. The basic cell of VCG and PPC consists of one AND gate and one XOR gate respectively. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields GF($2^4$). Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper uses the VCGs and PPCS repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSL.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.76-81
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• 2006

Recently, Finite field is applied the cryptography in the modern multimedia communication. Especially, block codes such as Elliptic Curve Cryptosystem and Reed-Solomon code among the error correcting codes are defined with finite field. Also, finite field algorithm is conducting the research actively because many kind of application parts need the real time operating ability therefore the exclusive hardware have been implementing. In this paper, we proposed the inverse finite field algorithm over GF($2^8$) using finite composite field and implemented in a hardware, and then compare this hardware with the currently used 'Itoh and Tsujii' hardware in respect to structure, area and computation time. Furthermore, this hardware was inserted into the AES SubBytes block and implemented on FPGA emulator board to confirm that the superiority of the proposed algorithm through the performance evaluation.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Convergence Security Journal
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• v.7 no.3
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• pp.31-37
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• 2007

There are many investigations about the security on RFID system to protect privacy. It is important to mutual authentication of the security on RFID system. The protocol for mutual authentication use light-weight operation such as XOR operation, hash function and re-encryption. However, the protocol for authentication and privacy is required more complicated cryptography system. In this paper, we propose a mutual authentication protocol using finite field GF($2^n$) for a authentication and are a safety analysis about various attacks.