• Title/Summary/Keyword: 유전자 알고리즘 프로세서

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Gene Expression Data Analysis Using Parallel Processor based Pattern Classification Method (병렬 프로세서 기반의 패턴 분류 기법을 이용한 유전자 발현 데이터 분석)

  • Choi, Sun-Wook;Lee, Chong-Ho
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.46 no.6
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    • pp.44-55
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    • 2009
  • Diagnosis of diseases using gene expression data obtained from microarray chip is an active research area recently. It has been done by general machine learning algorithms, because it is difficult to analyze directly. However, recent research results about the analysis based on the interaction between genes is essential for the gene expression analysis, which means the analysis using the traditional machine learning algorithms has limitations. In this paper, we classify the gene expression data using the hyper-network model that considers the higher-order correlations between the features, and then compares the classification accuracies. And also, we present the new hypo-network model that improve the disadvantage of existing model, and compare the processing performances of the existing hypo-network model based on general sequential processor and the improved hypo-network model implemented on parallel processors. In the experimental results, we show that the performance of our model shows improved and competitive classification performance than traditional machine learning methods, as well as, the existing hypo-network model. We show that the performance is maximized when the hypernetwork model is implemented on our parallel processors.

A Load Balancing Technique Combined with Mean-Field Annealing and Genetic Algorithms (평균장 어닐링과 유전자 알고리즘을 결합한 부하균형기법)

  • Hong Chul-Eui;Park Kyeong-Mo
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.8
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    • pp.486-494
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    • 2006
  • In this paper, we introduce a new solution for the load balancing problem, an important issue in parallel processing. Our heuristic load balancing technique called MGA effectively combines the benefit of both mean-field annealing (MFA) and genetic algorithms (GA). We compare the proposed MGA algorithm with other mapping algorithms (MFA, GA-l, and GA-2). A multiprocessor mapping algorithm simulation has been developed to measure performance improvement ratio of these algorithms. Our experimental results show that our new technique, the composition of heuristic mapping methods improves performance over the conventional ones, in terms of solution quality with a longer run time.

A 2-Dimension Torus-based Genetic Algorithm for Multi-disk Data Allocation (2차원 토러스 기반 다중 디스크 데이터 배치 병렬 유전자 알고리즘)

  • 안대영;이상화;송해상
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.41 no.2
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    • pp.9-22
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    • 2004
  • This paper presents a parallel genetic algorithm for the Multi-disk data allocation problem an NP-complete problem. This problem is to find a method to distribute a Binary Cartesian Product File on disk-arrays to maximize parallel disk I/O accesses. A Sequential Genetic Algorithm(SGA), DAGA, has been proposed and showed the superiority to the other proposed methods, but it has been observed that DAGA consumes considerably lengthy simulation time. In this paper, a parallel version of DAGA(ParaDAGA) is proposed. The ParaDAGA is a 2-dimension torus-based Parallel Genetic Algorithm(PGA) and it is based on a distributed population structure. The ParaDAGA has been implemented on the parallel computer simulated on a single processor platform. Through the simulation, we study the impact of varying ParaDAGA parameters and compare the quality of solution derived by ParaDAGA and DAGA. Comparing the quality of solutions, ParaDAGA is superior to DAGA in all cases of configurations in less simulation time.

An Implementation of Evolvable Adaptive Image Preprocessing Filter (진화적응성을 갖는 영상 전처리 필터 구현)

  • Lee, Seung-Young;Jun, In-Ja;Rhee, Phill-Kyu
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2783-2787
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    • 2002
  • 최근 멀티미디어 및 통신의 발달로 인하여 영상 정보를 이용한 응용시스템이 많이 연구되고있다. 중간 전달 매체를 이용한 응용시스템으로의 영상 정보를 전달과정에서 잡영(noise) 이 포함되어 시스템의 성능을 저하시키게 된다. 또한 잡영은 임의의 형태이기 때문에 상황에 따라 적합한 필터를 선택하기는 쉽지 않다. 본 논문에서는 유전자 알고리즘 프로세서를 이용하여 필터들의 구성 및 파라미터를 조절하여 임의의 잡영에 진화적응적인 능력을 가지는 영상 전처리 필터를 구현하였다. 주파수 영역의 잡영에 대해서는 하드웨어에 적합하고 구현이 용이한 멀티밴드필터(Multi-Band filter)를 설계하여 사용하였다. 시스템은 유전자알고리즘과 필터블록에 대해서는 하드웨어(FPCA)로 구현하였고 적합도 평가는 PC 기반으로 수행하였다. 실험결과 순수 PC기반의 시뮬레이션에 비해 속도향상 및 성능면에서도 만족할 만한 결과를 얻었다.

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Implementation of GA Processor with Multiple Operators, Based on Subpopulation Architecture (분할구조 기반의 다기능 연산 유전자 알고리즘 프로세서의 구현)

  • Cho Min-Sok;Chung Duck-Jin
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.5
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    • pp.295-304
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    • 2003
  • In this paper, we proposed a hardware-oriented Genetic Algorithm Processor(GAP) based on subpopulation architecture for high-performance convergence and reducing computation time. The proposed architecture was applied to enhancing population diversity for correspondence to premature convergence. In addition, the crossover operator selection and linear ranking subpop selection were newly employed for efficient exploration. As stochastic search space selection through linear ranking and suitable genetic operator selection with respect to the convergence state of each subpopulation was used, the elapsed time of searching optimal solution was shortened. In the experiments, the computation speed was increased by over $10\%$ compared to survival-based GA and Modified-tournament GA. Especially, increased by over $20\%$ in the multi-modal function. The proposed Subpop GA processor was implemented on FPGA device APEX EP20K600EBC652-3 of AGENT 2000 design kit.

Comparison of Genetic Algorithms and Simulated Annealing for Multiprocessor Task Allocation (멀티프로세서 태스크 할당을 위한 GA과 SA의 비교)

  • Park, Gyeong-Mo
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.9
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    • pp.2311-2319
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    • 1999
  • We present two heuristic algorithms for the task allocation problem (NP-complete problem) in parallel computing. The problem is to find an optimal mapping of multiple communicating tasks of a parallel program onto the multiple processing nodes of a distributed-memory multicomputer. The purpose of mapping these tasks into the nodes of the target architecture is the minimization of parallel execution time without sacrificing solution quality. Many heuristic approaches have been employed to obtain satisfactory mapping. Our heuristics are based on genetic algorithms and simulated annealing. We formulate an objective function as a total computational cost for a mapping configuration, and evaluate the performance of our heuristic algorithms. We compare the quality of solutions and times derived by the random, greedy, genetic, and annealing algorithms. Our experimental findings from a simulation study of the allocation algorithms are presented.

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Implementation of Genetic Algorithm Processor based on Hardware Optimization for Evolvable Hardware (진화형 하드웨어를 위한 하드웨어 최적화된 유전자 알고리즘 프로세서의 구현)

  • Kim, Jin-Jeong;Jeong, Deok-Jin
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.3
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    • pp.133-144
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    • 2000
  • Genetic Algorithm(GA) has been known as a method of solving large-scaled optimization problems with complex constraints in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementations of Genetic Algorithm Processors(GAP) are focused on in recent studies. In this paper, a hardware-oriented GA was proposed in order to save the hardware resources and to reduce the execution time of GAP. Based on steady-state model among continuos generation model, the proposed GA used modified tournament selection, as well as special survival condition, with replaced whenever the offspring's fitness is better than worse-fit parent's. The proposed algorithm shows more than 30% in convergence speed over the conventional algorithm in simulation. Finally, by employing the efficient pipeline parallelization and handshaking protocol in proposed GAP, above 30% of the computation speed-up can be achieved over survival-based GA which runs one million crossovers per second (1㎒), when device speed and size of application are taken into account on prototype. It would be used for high speed processing such of central processor of evolvable hardware, robot control and many optimization problems.

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Design of state machine using Evolvable Hardware and Genetic Algorithm Processor (GAP와 진화 하드웨어를 이용한 State Machine설계)

  • 김태훈;선흥규;박창현;이동욱;심귀보
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2002.05a
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    • pp.179-182
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    • 2002
  • GA(Genetic Algorithm)는 자연계 진화를 모방한 계산 알고리즘으로서 단순하고 응용이 쉽기 때문에 여러 분야에 전역적 최적해 탐색에 많이 사용되고 있다. 최근에는 하드웨어를 구성하는 방법의 하나로서 사용되어 진화하드웨어라는 분야를 탄생시켰다. 이와 함께 GA의 연산자체를 하드웨어로 구현하는 GA processor(GAP)의 필요성도 증가하고 있다. 특히 진화하드웨어를 소프트웨어상에서 진화 시키는 것이 아닌 GAP에 의해 진화 시키는 것은 독립된 구조의 진정한 EHW 설계에 필수적이 될 것이다. 본 논문에서는 GAP 설계 방법을 제안하고 이를 이용하여 진화하드웨어로 State machine을 구현하고자 한다. State machine의 경우 구조상 피드백이 필요하기 때문에 가산기나 멀티플렉서보다는 훨씬 복잡하고 설계가 까다로운 구조이다. 제안된 방법을 통하여 명시적 설계가 어려운 하드웨어 설계에 GAP를 이용한 하드웨어의 진화에 적용함으로써 그 유용성을 보인다.

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Multi-FNN Identification by Means of HCM Clustering and ITs Optimization Using Genetic Algorithms (HCM 클러스터링에 의한 다중 퍼지-뉴럴 네트워크 동정과 유전자 알고리즘을 이용한 이의 최적화)

  • 오성권;박호성
    • Journal of the Korean Institute of Intelligent Systems
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    • v.10 no.5
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    • pp.487-496
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    • 2000
  • In this paper, the Multi-FNN(Fuzzy-Neural Networks) model is identified and optimized using HCM(Hard C-Means) clustering method and genetic algorithms. The proposed Multi-FNN is based on Yamakawa's FNN and uses simplified inference as fuzzy inference method and error back propagation algorithm as learning rules. We use a HCM clustering and Genetic Algorithms(GAs) to identify both the structure and the parameters of a Multi-FNN model. Here, HCM clustering method, which is carried out for the process data preprocessing of system modeling, is utilized to determine the structure of Multi-FNN according to the divisions of input-output space using I/O process data. Also, the parameters of Multi-FNN model such as apexes of membership function, learning rates and momentum coefficients are adjusted using genetic algorithms. A aggregate performance index with a weighting factor is used to achieve a sound balance between approximation and generalization abilities of the model. The aggregate performance index stands for an aggregate objective function with a weighting factor to consider a mutual balance and dependency between approximation and predictive abilities. According to the selection and adjustment of a weighting factor of this aggregate abjective function which depends on the number of data and a certain degree of nonlinearity, we show that it is available and effective to design an optimal Multi-FNN model. To evaluate the performance of the proposed model, we use the time series data for gas furnace and the numerical data of nonlinear function.

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VLSI Implementation of Adaptive mutation rate Genetic Algorithm Processor (자가적응 유전자 알고리즘 프로세서의 VLSI 구현)

  • 허인수;이주환;조민석;정덕진
    • Proceedings of the IEEK Conference
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    • 2001.06c
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    • pp.157-160
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    • 2001
  • This paper has been studied a Adaptive Mutation rate Genetic Algorithm Processor. Genetic Algorithm(GA) has some control parameters such as the probability of bit mutation or the probability of crossover. These value give a priori by the designer There exists a wide variety of values for for control parameters and it is difficult to find the best choice of these values in order to optimize the behavior of a particular GA. We proposed a Adaptive mutation rate GA within a steady-state genetic algorithm in order to provide a self-adapting mutation mechanism. In this paper, the proposed a adaptive mutation rate GAP is implemented on the FPGA board with a APEX EP20K600EBC652-3 devices. The proposed a adaptive mutation rate GAP increased the speed of finding optimal solution by about 10%, and increased probability of finding the optimal solution more than the conventional GAP

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