• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.4
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• pp.68-77
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• 2008

When we design the grounding grid, dangerous voltage IEEE Std. 80 method has been commonly used in the domestic area. However there is not appropriative examination of ground design environment. So in this paper, we examined of IEEE Std. 80 touch voltage method's marginal utility and we induced corrective factor for those problems by comparison between IEEE Std. 80 touch voltage value and simulation experimentation value. Moreover, Logistic model's corrective factor we proved the maximum accidental error has reduced less than 10[%].

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.89-97
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• 2003

High frequency common mode voltage produced by PWM inverter fed Induction motor is a major cause of conducted EMI, creation motor ground currents, bearing currents and other harmful products. The zero switching states of inverter control invoke large in comparison with the non-zero switching state of Inverter control. We proposed a common mode voltage reduction method based on sinusoidal PWM technique. PWM signal are generated by comparing respective sinusoidal reference signal with three triangular carrier wave displaced of 120$^{\circ}$. Simulation and experimenta1 result show that common mode voltages in the proposed PWM technique are reduced by approximate 66% more than conventional FWM technique.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.58-64
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• 1984

A simple model for the impurity profile in an ion-implanted channel layer of an enhancement type IGFET is assumed and a simple expression for the threshold voltage derived by using the assumed impurity profile is analyzed in detail. Also, this simple model is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel devices. The error range of threshold voltage between gaussian-profile and box-profile is calculated in this paper and a new method of calculating the depth of ion-implanted Baler D is also introduced.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.71-72
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• 2006

플라스틱 기판 위에 유도 결합 플라즈마 화학적 기상 증착장치 (Inductively Coupled Plasma Chemicai Vapor Deposition, ICP-CVD) 를 사용하여 실리콘 산화막 ($SiO_2$)을 증착하고, 엑시머레이저 어널링 (Excimer Laser Annealing, ELA) 과 $N_{2}O$ 플라즈마 전처리를 통해, 전기용량-전압(Capacitance-Voltage, C-V) 특성과 항복 전압장 (Breakdown Voltage Field) 과 같은 전기적 특성을 개선시켰다. 에너지 밀도 $250\;mJ/cm^2$ 의 엑시머 레이저 어닐링은 실리콘 산화막의 평탄 전압 (Flat Band Voltage) 을 0V에 가까이 이동시키고, 유효 산화 전하밀도 (Effective Oxide Charge Density)를 크게 감소시킨다. $N_{2}O$ 플라즈마 전처리를 통해 항복 전압장은 6MV/cm 에서 9 MV/cm 으로 향상된다. 엑시머 레이저 어닐링과 $N_{2}O$ 플라즈마 전처리를 통해 평탄 전압은 -9V 에서 -1.8V 로 향상되고, 유효 전하 밀도 (Effective Charge Density) 는 $400^{\circ}C$에서 TEOS 실리콘 산화막을 증착하는 경우의 유효 전하 밀도 수준까지 감소한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.18-29
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• 2002

Generally, the single-stage power factor corrected converter has a problem of high dc link voltage. In the case of high line voltage, especially, the dc link voltage is verb high under the light load condition. To solve this problem, a new single stage power factor corrected AC/DC converter has been proposed. The proposed converter has huck topology as a power factor corrector. To prove feasibility of the proposed converter, the design example of the proposed converter has been presented. The design considerations and experimental results for the proposed converter have been shown. The experimental results show that the line input current harmonics can meet IEC1000-3-2 Class D requirements for the range of line input voltage from 90Vrms to 260Vrms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.849-851
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께 비에 대한 문턱전압이하 스윙 및 전도중심의 변화에 대하여 분석하고자한다. 문턱전압이하 스윙은 전도중심에 따라 변화하며 전도중심은 상하단의 산화막 두께에 따라 변화한다. 비대칭 이중게이트 MOSFET는 상단과 하단의 게이트 산화막 두께를 다르게 제작할 수 있어 문턱전압이하 스윙의 저하 등 단채널효과를 감소시키기에 유용한 소자로 알려져 있다. 본 연구에서는 포아송방정식의 해석학적 해를 이용하여 문턱전압이하 스윙을 유도하였으며 상하단의 산화막두께 비가 전도중심 및 문턱전압이하 스윙에 미치는 영향을 분석하였다. 결과적으로 문턱전압이하 스윙 및 전도중심은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 또한 채널길이 및 채널두께, 상하단게이트 전압 그리고 도핑분포함수의 변화에 따라 문턱전압이하 스윙 및 전도중심은 상호 유기적으로 변화하고 있다는 것을 알 수 있었다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.267-268
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• 2015

본 논문은 단일 스위치 공진형 컨버터에서 스위치의 전압 스트레스를 줄이는 설계 방법을 소개한다. 일반적으로 단일 스위치 공진형 컨버터는 입력 전압 대비 높은 전압이 스위치에 걸리므로 높은 입력 전압 응용에 제약이 있다. 따라서 본 논문에서는 스위치의 피크 전압을 줄이고자 3차 고조파를 주입한 전압 모양을 만들도록 스위치 주변의 LC 공진 회로를 설계한다. 이 설계 방식을 이용하면 영전압 스위칭이 가능할 뿐만 아니라 전압 스트레스를 입력 전압의 2.2배 정도로 줄일 수 있다. 또한, 설계 원칙에 따라 여러 토폴로지가 유도되며, 설계 예시를 통해 제안된 설계 방식의 효용성을 실험적으로 입증한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1289-1301
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• 2011

In this paper, flux estimation method at the Induction motor is applied to stability flux estimate of possibility in overall speed domain. angle operation has voltage and current and speed information using the Induction motor direct control method. Induction motor direct control is material to flux information. Exact flux estimation method to using current model flux estimator of low-speed domain and voltage model flux estimator of high-speed domain. Speed and current and flux controller using PI controller. And error of integral requital for add to Anti-Windup PI controller. Verified to performance of Current model Flux controller and voltage model flux controller using Matlab / Simulink. Analysis has parameter influence of direct vector control and indirect vector control at the Induction motor vector control. So, verified to minute control. Analyzed to simulation result and proof to validity of presented algorithm.

• Electric Engineers Magazine
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• s.126
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• pp.25-36
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• 1993

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.799-804
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• 2016

To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.