• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.25 no.1
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• pp.13-23
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• 2015

The paper experimentally deals with the radial in-plane vibration characteristics of disk-shaped piezoelectric transducers. The radial in-plane motion, which is induced due to Poisson's ratio in the piezoelectric disk polarized in the thickness direction, was measured by using an in-plane laser vibrometer, and the natural frequencies were measured by using an impedance analyzer. The experimental results have been compared with theoretical predictions obtained by simplified theoretical and finite-element analyses. It appears that the fundamental mode of a piezoelectric disk transducer is a radial mode and its radial displacement distribution from the center to the perimeter is not monotonic but shows maximum slightly apart from the perimeter. The theoretically-calculated fundamental frequencies agree well with the finite-element results for small thickness-to-diameter ratio, and they are accurate within 7 % error for the ratio up to 0.4.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.942-946
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• 2009

A scan order converter has to be placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. Recently a hardware architecture has been proposed to implement a scan converter based on the single line memory. Since both read and write accesses happen at each cycle, however, the largest part of the entire power budget is occupied by the SRAM itself. In this paper, the data packing and unpacking procedure is inserted in the processing chain, such that the access frequency to the SRAM is reduced to 1/8 by adopting a packed larger data unit. The simulation results show that the resultant power consumption is reduced down to 16% for the SXGA resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1617-1620
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• 2007

This paper presents a magnetostrictive transpositioner and its fabrication process. To get a transposition movement without shifting or twisting, it is designed as an array type. To fabricate the suggested design, micromachining and selective DC magnetron sputtering processes are combined. TbDyFe film is sputter-deposited on the back side of the bulk micromachined transpositioner, with the condition as: Ar gas pressure below $1.2{\times}10^{-9}$ torr, DC input power of 180W and heating temperature of up to $250^{\circ}C$ for the wireless control of each array component. After the sputter process, magnetization and magnetostriction of each sample are measured. X-ray diffraction studies are also carried out to determine the film structure and thickness of the sputtered film. For the operation, each component of the actuator has same length and out-of-plane motion. Each component is actuated by externally applied magnetic fields up to 0.5T and motion of the device made upward movement. As a result, deflections of the device due to the movement for the external magnetic fields are observed.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2658-2661
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• 2004

압전 구동기는 전기적 에너지를 직접 동역학적 에너지로 변환하는 세라믹 구동기이다. 특히 압전 구동기의 개방 회로 시스템은 분자 구조 특성에 의해 비선형적인 히스테리시스 특성과 크리프 특성을 가진다. 이러한 비선형적 시스템을 작은 분해능으로 제어하는 경우 이에 따른 외란, 모델링의 불확실성 둥의 오차가 발생하게 된다. 따라서, 현재 이러한 비선형적 오차를 기존의 PID 및 최적제어를 사용하여 보상하는 방법에 대해서 많은 연구가 진행되고 있다. 본 논문에서는 압전 구동기 위치 결정 시스템 전체에 대해 LQG 제어 및 $H_{\infty}$ 제어를 적용하여 시뮬레이션을 실시하였다. 또한 본 논문은 시뮬레이션 결과를 바탕으로 실제 압전 구동기 위치 결정 시스템에 $H_{\infty}$ 제어를 적용하여 제안된 $H_{\infty}$ 제어기가 시스템 성능에 영향을 주는 외란, 모델링의 불확실성 등을 효과적으로 제거함을 보여준다.

• Proceedings of the KIEE Conference
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• 2008.09a
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• pp.67-68
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• 2008

전력량의 증가로 인한 대전류 측정의 요구와 전력 시스템의 디지털화에 부응하여 대전류 국가 표준 시스템의 측정 범위의 확장 및 전자식 전류변성기의 평가를 위해 구축된 40 kA급 전류변성기 비교 측정 시스템과 전자식 변성기 평가 시스템을 소개하였다. 또한 전자시변성기 평가시스템의 핵심 장비인 전압-전류 변환기에 대한 비오차 및 위상오차를 평가하였고, $200A{\sim}40kA$ 까지의 로고스키 코일을 평가하였다. 마지막으로 로고스키 코일 평가시의 불화도 요인으로 1차 코일의 위치, 대전류 발생 변압기와의 거리에 따른 측정 불확도를 평가하였다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.120-130
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• 1999

In this paper, we show that the instantaneous phase current of the bifiler-wound hybrid stepping motor is dependent of lead angle and that the information of motor position is obtained from the instantaneous phase current at ${\pi}/2$ by the theoretical formular and its computer simulation results. From the facts, we design the microcontroller-based motor position sensorless controller of optimal lead angle, which generates the excitation pulses for the closed-loop drives. The controller is consist of microcontroller which has the function of A/D converter, programmable input/output timer, and the transfer table which has the values of optimal lead angle depending on motor velocity, and ROM which has the transfer table of the values of lead angle depending on velocity of motor and the values of instantaneous phase current at ${\pi}/2$. From the design of microcontroller-based controller, we minimize the external interface circuit and obtain flexibility by changing the contents of ROM transfer tables and the control software. We confirm that the designed controller drives the bifilar-wound hybrid stepping motor is the mode of optimal lead angle by comparing the instananeous phase current experimental results and computer simulation results.