• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2507-2513
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• 2010

In this paper, we show that the shrinking generator with two LFSR whose characteristic polynomials are primitive is an interleaving generator and analyze phase shifts in shrunken sequence. Also for a given intercepted sequence of shrunken sequence, we propose. the method of reconstructing some deterministic bits of the shrunken sequence using phase shifts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2365-2373
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• 2012

To obtain Korea AS-level internet topology, we used three data sources, which include BGP data of UCLA IRL, IRR and IXP data. Using Internet topology generator models(Waxman, BA and GLP), we developed three graphs that have same number of nodes as Korea AS-level Internet. Then we compared each graph with the Korea AS-level Internet topology. Through this study we could find that the existing Internet topology generators can't simulate Korea AS-level internet.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.915-920
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• 2004

In this paper, we propose the new polyphase sequence with the best nonperiodic autocorrelation property in the viewpoint of the merit factors, which are important criteria for a nonperiodic autocorrelation property. We propose the general implementation of a polyphase sequence generator over an integer residue ring by using a linear feedback shift register(LFSR), in addition, we analyze the linear complexities of polyphase sequences based on the proposed implementation method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.661-670
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• 2013

In this paper, we propose the measurement techniques of mixed waveform. Mixed waveform has phase-continuous periodic waveform with fixed frequency signal and Linear Frequency Modulation(LFM) signal. This waveform is generated from a compact radar transmitter with frequency synthesizer and high power amplifier. Frequency synthesizer generates various signal waveform with continuos phase and high power amplifier amplify transmitting signal. First, we describe a compact radar transmitter with the phase-continuos signal and then verify the distortion characteristic of pulse compression by the mismatch of LFM waveform. Second, we describe three kinds of measurement techniques for measuring LFM waveform. These techniques include methods using signal analyzer, signal source analyzer and new methods using RF mixer and phase shifter. Finally, we verify the accuracy of the measurement technique from the pulse compression result of receiving signal.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.160-161
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• 2003

위상특이점이라고도 불리는 광 보텍스(optical vortex)를 포함한 빔은 파면의 특이성 때문에 많은 관심을 끌어왔다. 위상을 정의할 수 없는 위상특이점을 따라서는 빔의 동일위상파면이 소용돌이 형태를 가진다. 그 소용돌이 정도는 위상전하(topological charge) 라는 양으로 특징지을 수 있다. 광 보텍스는 선형 및 비선형적 특성에 대해 많은 연구가 이루어져왔다. 레이저 공진기를 변형하거나, 홀로그램이나 위상마스크에 레이저를 조사하여 보텍스를 발생시키는 방법 등의 여러 방법이 알려져 있다. (중략)

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1994.11a
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• pp.132-156
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• 1994

본 논문에서는 비선형 합성 함수를 이용하여 생성된 난수 계열의 특성을 분석한다. 먼저 트레이스 함수 등을 정의하고, 선형 복잡도 및 생성기 구조 분석시 요구되는 관련 이론을 도출하고, 특정 난수 계열이 주어진 경우 이계열을 생성할 수 있는 최소 길이의 LFSR을 합성할 수 있는 USR 합성 알고리듬을 제시한다. 동일한 계열을 위상 천이한 계열간의 비선형 결합으로 생성된 난수 계열과 다른 계열간의 비선형 결합으로 생성된 난수 계열에 대한 주기 및 선형 복잡도 등의 특성을 분석하고 생성기의 구조를 제시한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.848-855
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• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.199-205
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• 2011

This paper presents a QR decomposition processor by exploiting Givens rotation for the GDFE (Generalized Decision Feedback Equalizer). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining two-stage method (coarse and fine stage) and the fixed-width modified-Booth multiplier, we design an efficient QR decomposition processor. By simulations, it is shown that the proposed QR decomposition processor can be a feasible solution for GDFE.