• Title/Summary/Keyword: 위상오프셋

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Design and Performance Evaluation of an Advanced CI/OFDM System for the Reduction of PAPR and ICI (PAPR과 ICI의 동시 저감을 위한 개선형 CI/OFDM 시스템 설계와 성능 평가)

  • Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.6A
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    • pp.583-591
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    • 2008
  • OFDM (orthogonal frequency division multiplexing) has serious problem of high PAPR (peak-to-average power ratio). Recently, CI/OFDM (carrier interferometry OFDM) system has been proposed for the low PAPR. However, CI/OFDM system shows another problem of ICI because of phase offset mismatch due to the phase noise. In this paper, to simultaneously reduce the PAPR and ICI effects, we propose an A-CI/OFDM (advanced-CT/OFDM). This method improves the BER performance by use of the margin of phase offset at CI codes. Propose system to reduce the effect the phase noise, even though it shows a little bit higher PAPR than conventional CI/OFDM, so we apply the PTS among the PAPR reduction techniques to proposed system to mitigate this problem. Therefore, it improves the total BER performance because the proposed method can decrease the effect of phase noise and get the gain in PAPR reduction performance. From the simulation results, we can show the performance comparison between the conventional OFDM, CI/OFDM and A-CI/OFDM.

Development and Positioning Accuracy Assessment of Precise Point Positioning Algorithms based on GPS Code-Pseudorange Measurements (GPS 코드의사거리 기반 정밀단독측위(PPP) 알고리즘 개발 및 측위 정확도 평가)

  • Park, Kwan Dong;Kim, Ji Hye;Won, Ji Hye;Kim, Du Sik
    • Journal of Korean Society for Geospatial Information Science
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    • v.22 no.1
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    • pp.47-54
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    • 2014
  • Precise Point Positioning (PPP) algorithms using GPS code pseudo-range measurements were developed and their accuracy was validated for the purpose of implementing them on a portable device. The group delay, relativistic effect, and satellite-antenna phase center offset models were applied as fundamental corrections for PPP. GPS satellite orbit and clock offsets were taken from the International GNSS Service official products which were interpolated using the best available algorithms. Tropospheric and ionospheric delays were obtained by applying mapping functions to the outputs from scientific GPS data processing software and Global Ionosphere Maps, respectively. When the developed algorithms were tested for four days of data, the horizontal and vertical positioning accuracies were 0.8-1.6 and 1.6-2.2 meters, respectively. This level of performance is comparable to that of Differential GPS, and further improvements and fine-tuning of this suite of PPP algorithms and its implementation at a portable device should be utilized in a variety of surveying and Location-Based Service applications.

A Design of Voltage Controlled Oscillator and High Speed 1/4 Frequency Divider using 65nm CMOS Process (65nm CMOS 공정을 이용한 전압제어발진기와 고속 4분주기의 설계)

  • Lee, Jongsuk;Moon, Yong
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.107-113
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    • 2014
  • A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

A Low Phase-Noise Ka-Band Hybrid Frequency Synthesizer for Millimeter Wave Seeker (낮은 위상 잡음을 갖는 Ka 대역 밀리미터파 탐색기용 하이브리드 주파수 합성기)

  • Lim, Ju-Hyun;Han, Hae-Jin
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.11
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    • pp.1117-1124
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    • 2011
  • In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. We improved frequency synthesizer performance of phase noise, resolution and spurious using the DDS driven hybrid method The proposed frequency synthesizer has the bandwidth of 1 GHz, frequency switching time of below 9 ${\mu}s$, suppressed spurious level of below -68.9 dBc. phase noise of -113.58 dBc/Hz at offset 100 kHz and flatness of ${\pm}$0.7 dB.

Sub-1V Series-Tuned Differential Colpitts VCO with Quarter Wavelength Microstrip Line Current Sources (1/4 파장 마이크로스트립 라인을 전류원을 갖는 서브-1V 직렬공진 차동 콜피츠 전압제어 발진기)

  • Jeon, Man-Young
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.625-629
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    • 2014
  • This study derives the asymptotic phase noise formula of the oscillators perturbed by the colored noises. Based on the derived formula, this study presents a sub-1V series-tuned differential Colpitts VCO. The ADS simulation result on the phase noise shows that the presented VCO exhibits about 3dBc/Hz lower phase noise at the 1MHz offset frequency from the oscillation frequency of 4.8GHz than the existing series-tuned differential Colpitts VCO with the inductor current sources.

The Design of New Phase Noise Dielectric Resonator Parallel Feedback Oscillator (새로운 구조의 저 위상잡음 유전체 공진 병렬 궤환 발진기)

  • 전광일;박진우
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.947-954
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    • 1999
  • A new low phase noise Dielectric Resonator Parallel Feedback Oscillator(DRPFO) that is proposed in this paper has a simple structure so that it can be fabricated in low cost and with high performance. The proposed DRPFO is in a feedback loop oscillator configuration, which is composed of a low noise amplifier, a power amplifier, a power attenuator, a power divider and a parallel resonator feedback element that consists of a dielectric resonator coupled with two microstrip lines. The measured phase noise of DRPFO was less than -81 dBc/Hz at offset frequency 1 kHz of 10.75 GHz carrier frequency, and the frequency stability of DRPFO was less than $\pm$200 kHz over the temperature range of -40$^{\circ}$C to +60$^{\circ}$C.

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Low-Phase Noise Oscillator Using Substrate Integrated Waveguide and Complementary Split Ring Resonator (기판 집적형 도파관(SIW)과 Complementary Split Ring Resonator(CSRR)로 구현한 저위상 잡음 발진기 설계)

  • Park, Woo-Young;Lim, Sung-Joon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.4
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    • pp.468-474
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    • 2012
  • A low phase-noise microwave oscillator is presented by a substrate integrated waveguide(SIW) loading a complementary split ring resonator(CSRR) in this paper. The unloaded $Q$-factor of the SIW cavity is increased by loading a complementary split ring resonator(CSRR) and its value exhibits 1960. It is theoretically and experimentally demonstrated that the proposed circuit generates 11.3 dBm of output power at 9.3 GHz and a phase-noise of -127.9 dBc/Hz at 1-MHz offset.

Joint Estimation of Phase and Frequency Offsets using a Simple Interpolation of a DFT Algorithm in Burst MPSK Transmission (버스트 MPSK 전송에서 시스템 파라미터들의 동시 추정 성능의 개선을 위한 이산 푸리에 변환의 보간기법)

  • Hong, Dae-Ki;Lee, Yong-Jo;Hong, Dae-Sik;Kang, Chang-Eon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1A
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    • pp.51-57
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    • 2002
  • In this paper, a simple interpolation technique in a frequency domain is proposed for the discrete Fourier transform(DFT) algorithm. Frequency and phase resolution capabilities of the DFT algorithm can be significantly improved by the proposed interpolation technique without increase of a DFT size(the number of points for the DFT). The new technique uses a diving point in amplitude and phase spectrums. As an application, the technique can be used for joint estimation of fine frequency and phase offsets in burst mode digital transmission. Simulation results show that the joint estimator using the technique is robust to estimation errors.

Design and Performance Analysis of 60GHz Wireless Communication System for Low Power Consumption and High Link Quality (저전력 및 고품질의 60GHz대역 무선 통신 시스템 설계와 성능 분석)

  • Bok, Junyeong;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.2
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    • pp.209-216
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    • 2013
  • In this paper, we design and analyze digital retrodirective array antenna (RDA) system in 60GHz wireless communication for low power consumption and high quality. Digital RDA can automatically make beam toward source without information about the direction of incoming signal, this system is able to do low power communication thanks to increased signal to interference noise ratio (SINR) because making the beam toward source can reduce interference signals. The frequency offset seriously arises when millimetric wave band like 60GHz is used to communicate for high-speed transmission. The proposed system is robustly designed to frequency offset through designing digital phase lock loop in order to solve the problem of frequency offset. In this paper, we analyze the performance of the proposed system according to the number of array antenna and frequency offset. striking space.

Design of Carrier Recovery Circuit for High-Order QAM - Part I : Design and Analysis of Phase Detector with Large Frequency Acquisition Range (High-Order QAM에 적합한 반송파 동기회로 설계 - I부. 넓은 주파수 포착범위를 가지는 위상검출기 설계 및 분석)

  • Kim, Ki-Yun;Cho, Byung-Hak;Choi, Hyung-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.4
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    • pp.11-17
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    • 2001
  • In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.

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