• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.679-679
• /
• 2013

태양전지는 계속되는 유가상승과 무소음 무공해의 녹색에너지원이라는 점에서 각광받고 있다. 더욱이 발전단가가 높기 때문에 특히 저가의 다결정 실리콘 태양전지의 연구가 활발히 진행되고 있다. 태양전지의 texturing 공정은 광 포획 효과를 극대화 시킨다. 이에 따라 웨이퍼 표면에 텍스쳐를 형성하여, 광학적 손실을 줄이는데, 일반적으로 alkaline etching (WET) 공정과 reactive ion etching (RIE) 공정이 사용된다. 본 연구에서는 RIE, WET 공정을 사용하여 만든 texturing 구조의 태양전지를 모듈 공정 진행 전 특성평가를 한 후 다시 모듈 공정 후 특성평가를 진행하였다. 특성평가는 태양전지의 전류-전압 곡선을 통해 개방전압, 단락전류, 곡선인자 을 측정하고, 파장에 따른 양자효율 및 반사율을 측정하였다. 또한 태양전지의 전기에너지를 가하여 생성되는 전계발광 현상과 NIR camera를 이용하여 Grain의 Dark Area 및 Micro crack을 검출하였다. 이와 같은 모듈 공정 전/후 특성을 측정하고, 이를 비교 분석하여 BIPV 적용 시 태양전지의 동작특성을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.11
• /
• pp.2385-2390
• /
• 2009

N-doped ZnO thin films with c-axis preferred orientation were prepared on p-Si(100) wafers, using an RF magnetron sputter deposition. For ZnO deposition, $N_2O$ gas was employed as a dopant source and various deposition conditions such as $N_2O$ gas fraction and RF power were applied. The depth pofiles of the nitrogen [N] atoms incorporated into the ZnO thin films were investigated by Auger Electron Spectroscopy(AES) and the nano-scale structural characteristics of the N-doped ZnO thin films were also investigated by a scanning electron microscope (SEM) technique.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.23 no.3
• /
• pp.129-134
• /
• 2013

Sapphire wafers are used as an important substrate for the production of blue LED (light emitting diode) and the LED's performance largely depends on the quality of the sapphire single crystals. There are several crystal growth methods for sapphire crystals and Kyropoulos method is an efficient way to grow large diameter and high-quality sapphire single crystals with low dislocation density. During Kyropoulos growth, the convection of molten melt is largely influenced by the hot zone geometry such as crucible shape, heater and refractory arrangements. In this study, CFD (computational fluid dynamics) simulations were performed according to the bottom/side ratios (per unit of the crucible surface area) of heaters. And, based on the results of analysis, the molten alumina flows and remelting phenomena were analyzed.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.3
• /
• pp.83-88
• /
• 2020

The evolution of smartphones has led to numerous researches in the mechanical behavior of flexible devices. Due to the nano-size of the thin flexible film, nanoindentation is widely used to evaluate its mechanical behaviors, such as elastic modulus, and hardness. However, the commonly used Oliver-Pharr method is not suited for analyzing the indentation force-depth curves of hard films on soft substrates, as the effects of soft substrate is not considered theoretically. In this study, the elastic modulus of the thin film was evaluated with references to other reported models which include the substrate effect, and with calibration of the indentation depth for the pile-ups between the indenter and test surface. We fabricated test samples by deposition of amorphous metal film on polyimide and silicon wafers for verification of modified models.

• Korean Journal of Materials Research
• /
• v.8 no.7
• /
• pp.579-583
• /
• 1998

Silicide layer structures, agglomeration of silicide layers, and dopant redistributions for the Co/Ti bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The $CoSi_2$ phase transition temperature is higher and agglomeration of the silicide layer occurs more severely for the Co/Ti bilayer on the doped polycrystalline Si substrate than on the single Si substrate. Also, dopant loss by outdiffusion is much more significant on the doped polycrystalline Si substrate than on the single Si substrate. All of these differences are attributed to the grain boundary diffusion and heavier doping concentration in the polycrystalline Si. The layer structure after silicidation annealing of Co/ Tildoped - polycrystalline Si is polycrystalline CoSi,/polycrystalline Si, while that of Co/TiI( 100) Si is Co- Ti- Si/epi- CoSi,/(lOO) Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.247-247
• /
• 2010

CdTe는 최근 적외선 검출기 개발에 응용하기 위해 활발한 연구가 진행 중인데 이는 HgCdTe(MCT)와 격자 불일치가 0.3% 이하로 대구경 단결정 MCT박막 제작이 용이하기 때문이다. 본 연구에서는 MBE 공정으로 GaAs 물질이 완충층으로 증착된 Si(100)기판을 사용하여 CdTe 물질과 Si기판간의 격자 불일치를 줄여 대면적 CdTe 단결정 박막을 얻고자 완충층의 두께별 결정성 및 표면 특성을 보았다. CdTe 박막의 증착은 Metal Organic Chemical Vapor Deposition system (MOCVD)를 이용하였고 실험결과 2nm의 GaAs 완충층이 사용된 박막에서 단결정 CdTe(400) 박막이 성장 되었으며, GaAs 완충층의 두께가 증가 함에 따라 $1{\mu}m$ 완충층에서는 다결정 박막이 성장 되었다. 본 연구결과는 Si 기판에 성장된 단결정 CdTe층을 이용 대면적 HgCdTe웨이퍼의 제조에 널리 이용 될 수 있으리라 여겨진다.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.10
• /
• pp.113-123
• /
• 1990

Tungsten film was deposited on the single crystal silicon wafer in a low pressure chemical vapor deposition reactor from silane and tungsten hexafluoride in the temperature range of $250-400^{\circ}C$ Deposition rate was found to be determined by the mass transfer rate of reactants from the gas phase to the safter surface. It was found out that tungsten films deposited contained about 3 atomic $\%$ of silicon and that the crystallinity and the grain size increased as the deposition temperature was increased. The resistivity of the film was measured to be in the range of $7~25{\mu}{\Omega}-cm$ and decreased with increasing deposition temperature. The adhesion of the tungsten film on a silicon surface was measured by the tape peel off test and it was improved with increasing deposition temperature. From the analysis of the gas composition, the reaction pathway to form $SiF_{4}$ and $H_{2}$ was found to be more favorable than HF formation.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.248-248
• /
• 1999

현재 반도체 공정에서 사용하는 건식식각 공정은 고밀도 프라즈마를 사용한 플라즈마 장비를 사용하는 경향이 증대되고 있으며 이와 같은 고밀도 플라즈마 장비의 사용은 반도체 소자의 최소 선폭(CD)이 deep sub-micron으로 감소하고 반면 실리콘 웨이퍼의 크기는 8인치 직경이상으로 증가하여 가고 있어서 그 필요성이 더욱 더 증가되고 있다. 특히 TFT-LCD를 비롯한 PDP, 그리고 FED 등과 같은 여러 가지 형태의 평판 디스플레이의 제조공정에 있어서도 실리콘 기판에 비하여 대면적의 기판을 이용하고 또한 사각형 형태의 시편공정이 요구되므로 평판 디스플레이에서도 고밀도의 균일한 플라즈마 유지가 중요하다. 따라서, 본 실험에서는 여러 가지 형태의 영구자석 및 전자석의 세기 및 배열이 유도결합형 플라즈마에 미치는 효과(plasma&etch uniformity, etch rate, etc.)를 살펴보기 위해서, 유도결합형 플라즈마 chamber(210mm$\times$210mm) 내부에 magnetic cusping을 위한 영구자석용 하우스를 제작하여 표면에서 3000Gauss의 자장세기를 갖는 소형영구자석을 부착하였으며,외벽에는 chamber와 같이 사각형태로 40회 감겨진 50cm$\times$50cm 의 크기로 chamber 상하에 1개씩 Helmholtz 코일 형태로 설치하였다. 식각가스로는 Cl2, HBr, 그리고 BCl3 gas를 이용하여 axial magnet과 multidipole magnet 유무에 따른 반응성 gas의 polysilicon 식각특성을 살펴보았으며, 또한 electrostatic probe(ESP, Hiden Analytic미)를 이용하여 이들 반응성 gas에 대한 magnetically enhanced inductively coupled plasma의 특성분석을 수행하였따. Cl2, HBr, BCl3의 반응성 식각가스 조합을 이용하여 polysilicon의 식각속도 및 식각선택도를 관찰한 결과, 어떠한 자장도 가하지 않은 경우에 비해 gas의 분해율이 가장 높은 영구자석과 전자석의 조합에서 가장 높은 식각도가 관찰되었다. 특히 pure Cl2 플라즈마의 경우, Axial 방향의 전자석만을 가한 경우 식각속도에 있어서는 큰 증가를 보였으나, 식각균일도(식각균일도:8.8%)는 다소 감소하였으며, Axial 방향의 전자석과 영구자석을 조합한 경우 가장 높은 식각속도를 얻었으며, 식각균일도는 Axial 방향의 전자석만을 사용하였을 경우와 비교하여 향상되었다.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.1 s.343
• /
• pp.33-40
• /
• 2006

This paper presents a novel surface acoustic wave (SAW)-based pressure sensor, which is composed of single phase unidirectional transducer (SPUDT), three reflectors, and a deep etched substrate for bonding underneath the diaphragm. Using the coupling of modes (COM) theory, the SAW device was simulated, and the optimized design parameters were extracted. Finite Element Methods (FEM) was utilized to calculate the bending and stress/strain distribution on the diaphragm under a given pressure. Using extracted optimal design parameters, a 440 MHz reflective delay line on 41o YX LiNbO3 was developed. High S/N ratio, shan reflection peaks, and small spurious peaks were observed. The measured S11 results showed a good agreement with simulated results obtained from coupling-of-modes (COM) modeling and Finite Element Method (FEM) analysis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.3
• /
• pp.271-277
• /
• 2004

A Si(Silicon) MEMS(Micro Electro Mechanical System) package using a doped lossy Si carrier for CPW(Coplanar Waveguide) MMICs(Microwave and Millimeter-wave Integrated Circuits) is proposed in order to reduce parasitic problems of leakage, coupling and resonance. The proposed chip-carrier scheme is verified by fabricating and measuring a GaAs CPW on the two types of carriers(conductor-back metal, doped lossy Si) in the frequency from 0.5 to 40 ㎓. The proposed MEMS package using the lightly doped lossy(15 Ω$.$cm) Si chip-carrier and the HRS(High Resistivity Silicon, 15 ㏀$.$cm) shows the optimized loss and parasitic problems-free since the doped lossy Si-carrier effectively absorbs and suppresses the resonant leakage. The Si MEMS package for CPW MMICs has an insertion loss of only - 2.0 ㏈ and a power loss of - 7.5 ㏈ at 40 ㎓.