• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.22 no.11
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• pp.760-766
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• 2010

Excessive heat occurs during semiconductor manufacturing process. Thus, precise control of temperature is required to maintain constant chamber-temperature and also wafer-temperature in the chamber. Compared to an industrial chiller, semiconductor chiller's power consumption is very high due to its continuous operation for a year. Considering the high power consumption, it is necessary to develop an energy efficient chiller by optimizing operation control. Therefore, in this study, a semiconductor chiller is experimentally investigated to suggest energy-saving direction by conducting load change, temperature rise and fall and control precision experiments. The experimental study shows the cooling capacity of dual-channel chiller rises over 30% comparing to the conventional chiller. The time and power consumption in the temperature rising experiment are 43 minutes and 8.4 kWh, respectively. The control precision is the same as ${\pm}1^{\circ}C$ at $0^{\circ}C$ in any cases. However, it appears that the dual channel's control precision improves to ${\pm}0.5^{\circ}C$ when the setting temperature is over $30^{\circ}C$.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1884-1886
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• 2005

KrF 펄스 레이저 증착법(pulsed laser deposition: PLD)으로 ZnO 박막을 증착하여 평판 디스플레이 소자 구동용 박막 트랜지스터(thin film transistor) 소자를 제작하였다. 전도성이 높은 실리콘웨이퍼(c-Si, 하부전극) 기판 위에 LPCVD 법으로 silicon nitride 박막을 절연막으로 형성하고, 다양한 공정 조건에서 펄스 레이저 증착법으로 제작한 ZnO 박막을 증착하여 채널층으로 하였으며, Al 박막을 증착하고 패터닝하여 소스 및 드레인 전극으로 하였다. ZnO 박막의 증착 시에 기판 온도를 다양하게 조절하고 산소 분압을 변화시켜 ZnO 박막의 특성을 조절하였다. 제작된 박막의 표면특성은 AFM(atomic force microscopy)로 분석하고, 결정특성은 XRD(X-ray diffraction)로 조사하였다. ZnO 박막의 전기적 특성은 Hall-van der Pauw 법으로 측정하였고, 광학 투과도(optical transparency)를 UV-visible photometer로 조사하였다. ZnO-TFT 소자는 $10^6$ 수준의 on-off ratio와 $2.4{\sim}6.1cm^2/V{\cdot}s$의 전계효과이동도(field effect mobility)를 보였다.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1932-1934
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• 2003

본 논문은 신경전달물질 중 우울증, 신부전증의 지표 물질인 세로토닌의 농도를 극미량의 시료를 사용하여 정량할 수 있는 방법을 개발하기 위해 초소형 효소 고정화 전극을 개발하였다. 전극은 실리콘 웨이퍼 상에 반도체 공정을 이용하여 마이크로 크기의 Pt 박막 전극을 제작하였고, 전기화학적 방법으로 pyrrole 단량체를 Pt 전극 상에 순환전압전류법을 이용하여 산화적으로 전기 중합하였다. 효소의 고정은 일정 전압을 인가한 시간대 전류법으로 고정화하였다. 제작된 전극은 시간대 전류법으로 세로토닌의 농도에 따른 감도를 측정하였다. 세로토닌의 농도 범위 $1.0{\mu}mol/L{\sim}10mmol/L$에서의 감도는 $7.0{\mu}$A/decade를 나타내었으며, 실험결과에 따라 전극의 표면에서 발생하는 전류는 세로토닌의 농도에 비례함을 알 수 있었다. 전극의 표면분석은 Scanning Electron Microscopy(SEM), Energy Dispersive X-ray Spectroscopy(EDX) 그리고 Auger Electron Spectroscopy(AES)를 이용하여 분석하였다.

• Korean Journal of Optics and Photonics
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• v.7 no.2
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• pp.150-156
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• 1996

RWG MQW-LD has been made with our vertical LPE system from the optimal design condition for the RWG MQW-LD to be activated as weakly index-guided LD. Through several experiments we have established the growth condition which can be used through to grow the MQW-DH wafer and to control the thickness of MQW layer to ~200$\AA$. 4 ${\mu}{\textrm}{m}$-thickness of the ridge pattern has been formed through the photolithographic process on the MQW-DH wafer grown by the former condition, and then we have fabricated the RWG MQW-LD using it. From the result of measuring the electro-optical characteristics we can make sure that it can be lasing as lasing as laterally single mode at even more than $2.7I_{th}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.200.1-200.1
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• 2013

실리콘 태양전지 표면에는 구조적인 결함에 의해 소수 캐리어의 재결합이 일어난다. 재결합에 의해 캐리어의 반송자 수명은 줄어들게 되고, 태양전지의 효율은 감소하게 된다. 이를 줄이기 위해 태양전지 전 후면에 패시베이션을 하게 되는데, 이번 연구는 단결정 실리콘 태양전지 전면에 SiNx막을 증착함으로 수소 패시베이션이 반송자 수명에 미치는 영향에 대하여 연구하였다. 공정을 위해 $156{\times}156mm^2$, 200 ${\mu}m$, 0.5-3.0 ${\Omega}{\cdot}cm$ and p-type 단결정 실리콘 웨이퍼를 사용하였고, SiNx막을 올리기 전에 KOH 8.5% 용액으로 SDR을 실행하였다. RF-PECVD 장비로 SiNx 막을 증착하였고 증착 온도는 $200{\sim}400^{\circ}C$, 반응기 내부의 압력을 200~1,000 mtorr, SiH4/NH3/N2 각각의 가스 비율 조절, 그리고 플라즈마 RF power 변화시킴에 따라 증착된 SiNx막의 균일도 및 특성을 분석하였다. 반사광 측정 장비인 Reflectometer장비로 막의 두께와 굴절률, 반사율을 측정하였고, 반송자 수명을 측정하여 태양전지의 표면결함을 최대한 패시베이션 시켜주는 조건에 대한 연구를 수행하였다.

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.8 s.185
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• pp.178-184
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• 2006

Hot embossing is to fabricate desired pattern on the polymer substrate by pressing the patterned mold against the substrate which is heated above the glass transition temperature, and it is a high throughput fabrication method for bio chip, optical microstructure, etc. due to the simultaneous large area patterning. However, the bad pattern fidelity in large area patterning is one of the obstacles to applying the hot embossing technology for mass production. In the present study, PDMS pad was used as a cushion on the backside of the micro-patterned 4 inch Si mold to improve the pattern fidelity over the 4 inch PMMA sheet by increasing the conformal contact between the Si mold and the PMMA sheet. The pattern replicability improvement over 4 inch wafer scale was evaluated by comparing the replicated pattern height and depth for PDMS-cushioned Si mold against the rigid Si mold without PDMS cushion.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.41-46
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• 2017

This study aims to select suitable co-solvents and to obtain optimal process conditions in order to improve process efficiency and productivity through experimental results obtained under various experimental conditions for the etching and rinsing process using liquid carbon dioxide and supercritical carbon dioxide. Acetone was confirmed to be effective through basic experiments and used as the etching solution for MEMS-wafer etching in this study. In the case of using liquid carbon dioxide as the solvent and acetone as the etching solution, these two components were not mixed well and showed a phase separation. Liquid carbon dioxide in the lower layer interfered with contact between acetone and Mems-wafer during etching, and the results after rinsing and drying were not good. Based on the results obtained under various experimental conditions, the optimum process for treating MEMS-wafer using supercritical CO2 as the solvent, acetone as the etching solution, and methanol as the rinsing solution was set up, and MEMS-wafer without stiction can be obtained by continuous etching, rinsing and drying process. In addition, the amount of the etching solution (acetone) and the cleaning liquid (methanol) compared to the initial experimental values can be greatly reduced through optimization of process conditions.

• Korean Journal of Metals and Materials
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• v.49 no.9
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• pp.726-731
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• 2011

The present work shows how the flexural displacement-induced fracture strength of silicon devices, whose back surfaces have wafer grinding-induced scratch marks, depends on the crystallographic orientation. Experimental results indicate that silicon devices with scratch marks parallel to their lateral direction (i.e. reference axis in this work) are very susceptible to flexural fracture, as compared to devices with marks which deviated from the direction. The 3-point bending test shows that the fracture strength of silicon devices having marks which are oriented away from the reference axis is 2.6 times higher than that of devices with marks parallel to the axis. It was particularly interesting to see that silicon devices with identical preferred marks even reveal different fracture strengths, depending on whether the marks are involved in specific crystal planes such as {111} or {011}, called cleavage planes. This work demonstrates that silicon devices with the reference axis-aligned scratch marks not existing on such cleavage planes can have higher fracture strength approximately 20% higher than those existing on the planes.