• Title/Summary/Keyword: 용량 스케일링

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Throughput Scaling Law of Hybrid Erasure Networks Based on Physical Model (물리적 모델 기반 혼합 소거 네트워크의 용량 스케일링 법칙)

  • Shin, Won-Yong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.57-62
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    • 2014
  • The benefits of infrastructure support are shown by analyzing a throughput scaling law of an erasure network in which multiple relay stations (RSs) are regularly placed. Based on suitably modeling erasure probabilities under the assumed network, we show our achievable network throughput in the hybrid erasure network. More specifically, we use two types of physical models, a exponential decay model and a polynomial decay model. Then, we analyze our achievable throughput using two existing schemes including multi-hop transmissions with and without help of RSs. Our result indicates that for both physical models, the derived throughput scaling law depends on the number of nodes and the number of RSs.

Effect of Random Node Distribution on the Throughput in Infrastructure-Supported Erasure Networks (인프라구조 도움을 받는 소거 네트워크에서 용량에 대한 랜덤 노드 분포의 효과)

  • Shin, Won-Yong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.5
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    • pp.911-916
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    • 2016
  • The nearest-neighbor multihop routing with/without infrastructure support is known to achieve the optimal capacity scaling in a large packet-erasure network in which multiple wireless nodes and relay stations are regularly placed and packets are erased with a certain probability. In this paper, a throughput scaling law is shown for an infrastructure-supported erasure network where wireless nodes are randomly distributed, which is a more feasible scenario. We use an exponential decay model to suitably model an erasure probability. To achieve high throughput in hybrid random erasure networks, the multihop routing via highway using the percolation theory is proposed and the corresponding throughput scaling is derived. As a main result, the proposed percolation highway based routing scheme achieves the same throughput scaling as the nearest-neighbor multihop case in hybrid regular erasure networks. That is, it is shown that no performance loss occurs even when nodes are randomly distributed.

Improved Throughput Scaling of Large Ultra-Wide Band Ad Hoc Networks (거대 초 광 대역 애드 혹 네트워크에서의 개선된 용량 스케일링)

  • Shin, Won-Yong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.2
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    • pp.303-310
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    • 2014
  • We show improved throughput scaling laws for an ultra-wide band (UWB) ad hoc network, in which n wireless nodes are randomly located. First, we consider the case where a modified hierarchical cooperation (HC) strategy is used. Then, in a dense network of unit area, our result indicates that the derived throughput scaling depends on the path-loss exponent ${\alpha}$ for certain operating regimes due to the power-limited characteristics. It also turns out that the HC protocol is dominant for 2 < ${\alpha}$ < 3 while using the nearest multihop (MH) routing leads to a higher throughput for ${\alpha}{\geq}3$. Second, the impact and benefits of infrastructure support are analyzed, where m base stations (BSs) are regularly placed in UWB networks. In this case, the derived throughput scaling depends on ${\alpha}$ due to the power-limited characteristics for all operating regimes. Furthermore, it is shown that the total throughput scales linearly with parameter m as m is larger than a certain level. Hence, the use of either HC or infrastructure is helpful in improving the throughput of UWB networks in some conditions.

On the System Modeling and Capacity Scaling Law in Underwater Ad Hoc Networks (수중 애드 혹 네트워크에서의 시스템 모델링 및 용량 스케일링 법칙에 대하여)

  • Shin, Won-Yong;Kim, A-Jung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.4B
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    • pp.422-428
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    • 2011
  • In this paper, we introduce system and channel modeling for an underwater ad hoc acoustic network with n regularly located nodes, and then analyze capacity scaling laws based on the model. A narrow-band model is assumed where the carrier frequency is allowed to scale as a function of n. In the network, we characterize in attenuation parameter that depends on the frequency scaling as well as the transmission distance. A cut-set upper bound on the throughput scaling is then derived in extended networks having unit node density. Our result indicates that the upper bound is inversely proportional to the attenuation parameter, thus resulting in a power-limited network. Furthermore, we describe an achievable scheme based on the simple nearest-neighbor multi-hop (MH) transmission. It is shown under extended networks that the MH scheme is order-optimal for all the operating regimes expressed as functions of the attenuation parameter.

A Study on Tools for Agent System Development (클라우드 환경에서 오토 스케일링이 가능한 센서 데이터 수집 시스템 설계)

  • Park, Soo-Yong;Choi, Su-Min;Shin, Yong-Tae
    • Proceedings of the Korea Information Processing Society Conference
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    • 2020.05a
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    • pp.72-74
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    • 2020
  • 센서 네트워크의 센서 개수가 늘어나고 데이터 수집 주기가 짧아지며 데이터의 용량도 늘어남에 따라 데이터를 수집하는 중앙서버의 과부하가 걸리는 현상이 발생할 수 있다. 본 논문에서 제안하는 시스템은 센서 데이터를 수집하는 모듈을 컨테이너화 하여 쿠버네티스로 관리한다. 또한 쿠버네티스의 오토 스케일링 기능을 이용하여 데이터 수집 모듈의 과부하가 발생할 경우 자동으로 수집 모듈을 복사하여 scale out 할 수 있다.

Components sizing of powertrain for a Parallel Hybridization of the Mid-size Low-Floor Buses (중형저상버스 병렬형 하이브리드화를 위한 동력전달계 용량매칭)

  • Kim, Gisu;Park, Yeong-il;Ro, Yun-sik;Jung, Jae-wook
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.8
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    • pp.582-594
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    • 2016
  • Most studies on hybrid buses are on large-sized buses and not mid-sized low-floor buses. This study uses MATLAB simulation to evaluate the fuel efficiency of such buses powered by diesel. Based on the results, a hybrid electric vehicle system is recommended for the best combination of power and gear ratio. A parallel hybrid system was selected for the hybridization, which transmits front and rear wheel power independently. The necessary power to satisfy the target performance was calculated, and the applicable capacity area was designed. Dynamic programing was used to create and optimize a component sizing algorithm, which was used to scale the capacity of each component of the power source to satisfy the design criteria. The fuel efficiency rate, optimum power source capacity, and gear ratio can be improved by converting a conventional bus into a parallel hybrid bus.

Opportunistic Interference Management for Interfering Multiple-Access Channels (간섭 다중 접속 채널에서의 기회적 간섭 관리 기술)

  • Shin, Won-Yong;Park, Dohyung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37B no.10
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    • pp.929-937
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    • 2012
  • In this paper, we introduce three types of opportunistic interference management strategies in multi-cell uplink networks with time-invariant channel coefficients. First, we propose two types of opportunistic interference mitigation techniques, where each base station (BS) opportunistically selects a set of users who generate the minimum interference to the other BSs, and then their performance is analyzed in terms of degrees-of-freedom (DoF). Second, we propose a distributed opportunistic scheduling, where each BS opportunistically select a user using a scheduler designed based on two threshold, and then its performance is analyzed in terms of throughput scaling law. Finally, numerical evaluation is performed to verify our result.

Design and Implementation for Portable Low-Power Embedded System (저전력 휴대용 임베디드 시스템 설계 및 구현)

  • Lee, Jung-Hwan;Kim, Myung-Jung
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.7
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    • pp.454-461
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    • 2007
  • Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

A Design of Memory-efficient 2k/8k FFT/IFFT Processor using R4SDF/R4SDC Hybrid Structure (R4SDF/R4SDC Hybrid 구조를 이용한 메모리 효율적인 2k/8k FFT/IFFT 프로세서 설계)

  • 신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.430-439
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    • 2004
  • This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.