• The KIPS Transactions:PartA
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• 제16A권6호
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• pp.473-480
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• 2009

This paper is to enhance a color image running in the PXA255 ARM processor based on embedded linux environments. Retinex is one of the representative algorithm for image enhancement in the previous research. However, retinex is not suitable the run on the embedded system because of its long processing time. So, we proposed the image enhancement algorithm for embedded system, with less quantity of operation and the effect equivalent to retinex. To achieve this goal, we propose and implement the image enhancement algorithm, which utilizes the image formation model and gamma correction to be effective in a back-light and dark image. The proposed algorithm converts the color space from RGB to HSV, and then V and S channels are processed. In order to optimize the proposed method in the PXA255 ARM processor, quantity of calculation is reduced. The performance of the proposed algorithm was evaluated through qualitative method and quantitative method. The results show that brightness and contrast are improved with less quantity of operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제27권1A호
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• pp.80-88
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• 2002

Visual media(image, graphic, and video) processing poses challenge from several perpectives, specifically from the point of view of real-time implementation and scalability. There have been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. A variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. We have investigated a parallel processing system for improving the processing speed o f visual media related applications. The parallel processing system we proposed is similar to a pipelined memory stystem(MAMS). The multi-access memory system is made up of m memory modules and a memory controller to perform parallel memory access with a variety of combinations of 1${\times}$pq, pq${\times}$1, and p${\times}$q subarray, which improves both cost and complexity of control. Facial recognition, Phong shading, and automatic segmentation of moving object in image sequences are some that have been applied to the parallel processing system and resulted in faithful processing speed. This paper describes the parallel processing systems for the speedup and its utilization to three time-consuming applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권10호
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• pp.23-32
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• 2007

This paper proposes a reconfigurable parallel processor architecture which can efficiently implement various multimedia applications, such as 3D graphics, H.264/H.263/MPEG-4, JPEG/JPEG2000, and MP3. The proposed architecture directly connects memories and processors so that memory access time and power consumption are reduced. It supports floating-point operations needed in the geometry stage of 3D graphics. It adopts partitioned SIMD to reduce hardware costs. Conditional execution of instructions is used for easy development of parallel algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.1107-1111
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• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.

• Journal of the Korea Institute of Information Security & Cryptology
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• 제21권6호
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2007년도 학술대회 1부
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• pp.700-705
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• 2007

프로젝션 기반의 증강현실(AR, augmented reality) 시스템이란, 고화질의 가상 정보를 프로젝터를 통하여 정해진 공간에 정확하게 표시해 주는 시스템을 말한다. 대부분의 증강현실 시스템은 사용자의 몰입감을 높이기 위해 고화질, 대 화면을 제공하기 위한 디스플레이 장치를 사용하며, 영상처리의 복잡도에 따른 고성능의 프로세스 장치를 요구하기 때문에 데스크탑 환경에서 이루어졌다. 그러나, 데스크탑 환경에서의 증강현실 시스템은 휴대가 불편하다는 단점을 가진다. 최근 프로젝터의 소형화와 모바일 프로세서의 성능 향상은 휴대가 편리한 모바일 증강현실 시스템의 등장을 가능하게 하였다. 그러나, 모바일 증강현실 시스템은 작은 디스플레이를 이용하여 영상 정보를 표시해 주기 때문에 높은 해상도를 지원할 수 없으며, 사용자의 몰입감을 감소시킨다는 단점을 가지고 있다. 본 논문에서는 기존의 증강현실 시스템의 단점을 보완하기 위하여 PDA와 소형 프로젝터를 결합하여 프로젝션 기반의 휴대용 멀티미디어 플레이어($PMP^2$ : Portable Multimedia Player using Projection-Based augmented reality)라는 모바일 증강현실 시스템을 제안한다. $PMP^2$는 모바일 프로세서의 대표격이라 할 수 있는 PDA와 휴대용 소형 프로젝터를 이용함으로써 고화질, 대화면의 증강현실 영상을 다수의 사용자가 원하는 장소와 시간에 즐길 수 있도록 해 준다. $PMP^2$는 스크린의 기하 및 컬러에 따른 왜곡을 보상해 줌으로써, 특정한 스크린 없이도 언제 어디서나 사용자에게 정확한 영상을 제공해 준다. 본 논문에서는 다양한 시나리오에 대해 $PMP^2$의 유용성을 검증함으로써 모바일 환경에서의 프로젝션 기반의 증강 현실 시스템의 활용 가능성을 제시한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제18권3호
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• pp.177-183
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• 2018

Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.

• Journal of Advanced Navigation Technology
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• 제21권5호
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• pp.485-490
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• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2005년도 가을 학술발표논문집 Vol.32 No.2 (1)
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• pp.937-939
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• 2005

본 논문에서는 임베디드 프로세서인 ATmega128과 W3100A 이더넷 칩을 이용하여 범용 웹 모니터링 시스템을 구현하였다. 카메라를 이용한 동영상 오디오, RS-422 통신, 디지털/아날로그 신호의 입출력 등 다양한 제어 모니터링 정보를 통합하여 범용으로 사용할 수 있고, 소형, 저가, 저전력 소모가 가능하도록 설계, 구현하였다. 클라이언트 프로그램은 Java Applet으로 개발 하여 별도의 소프트웨어 설치 없이 웹브라우저를 통하여 접속되고, 원격지의 영상 및 각종 기기들의 상태를 실시간으로 모니터링하여 GUI기반의 각종 메뉴를 사용하여 원격 시스템을 편리하게 제어 할 수 있다.