• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.36-39
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• 2010

멀티 포맷 방송용 모니터는 SDI 신호뿐만 아니라 HDMI, DVI, Component, Composite로 전송되는 영상, 음성, 부가 데이터를 보여주는 모니터로 방송용 레퍼런스 모니터로 사용되고 있다. 특히 부가 데이터 중에서 Closed Caption의 경우 북미에서는 EIA-608과 EIA-708 두 가지 표준이 있고, 세부적으로 네 가지의 방법으로 전송되는데 일반적인 방송용 모니터에는 적용되어 있는 것이 극히 드물다. 또한 SDI 신호로 전송되는 Closed Caption 데이터를 Decoding하는 상용 IC는 거의 없는 수준이다. 이에 본 논문에서는 SDI로 전송되는 다양한 방식의 Closed Caption 데이터를 모두 표시하기 위한 방법을 제안하였다. 먼저 VBI (Vertical Blanking Interval) 에 아날로그 Waveform 형태로 입력되는 경우 데이터의 신뢰도를 높이기 위해 Clock Run In을 실시간으로 검출 할 수 있는 구조를 제안하고 FPGA (Field Programmable Gata Array)로 구현하였다. 또한 VANC (Vertical Ancillary Space)로 들어오는 Caption데이터의 경우 특히 EIA-708 처럼 많은 데이터가 입력되는 경우 실시간으로 처리하기 위해서 기존의 I2C와 같은 느린 전송 방법이 아닌 FPGA와 프로세서 간에 메모리를 직접 Access 할 수 있는 방법을 제안하였다. 본 논문에서 제안 한 방법을 FPGA로 구현하였고, 실제 미국이나 캐나다 방송국에서 사용하는 Caption 인코더 장비 뿐만아니라 방송 콘텐츠를 직접 이용하여 동작 상태를 검증하였다.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.119-122
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• 2000

인터넷이 일상생활에 다양하게 활용되면서 인터넷 채널을 통한 정보의 형태는 문자와 이미지 외에 음성, 오디오 신호 및 동영상 부분까지 확대되고 있다. 본 논문에서는 MPEG4-CELP를 인터넷 화상 통신의 음성 코덱용으로 사용하기 위한 최적화 기법 및 알고리듬의 개선을, DSP칩이 내장된 보드가 아닌 인터넷의 터미널로 사용되고 있는 펜티엄 프로세서를 장착한 PC에 초점을 맞추어 수행하였다. MPEG4-CELP VM C소스를 분석 및 프로파일(Profile)한 결과를 토대로 패라미터 추출을 위해 많은 연산을 수행하는 부호화기에 대해서 CPU상에 부하를 많이 주는 함수들을 제 1차 최적화 대상 함수들로 선정하고, CPU에 부하를 많이 주지는 않으나 호출되는 회수가 많은 함수를 2차 최적화 대상 함수로 선정해, C소스 레벨의 소프트웨어 파이프 라이닝(Software Pipelinging) 기법들을 적용하여 최적화를 수행하였다. 또한 1차 최적화 대상 함수의 경우에는 소프트웨어 파이프라이닝의 적용과 함께 연산량 감소를 위한 알고리듬 변형까지 수행하였다. 위의 과정을 거쳐 최적화 된 MPEG4-CELP는 펜티엄Ⅲ 450㎒ PC에서 음성을 부호화 하는데 원 VM소스에 비해 약 2배정도의 시간이 단축되는 것을 확인하였다.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2664-2666
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• 2005

In this paper, we develop the on board type image processing system using the CMOS sensor and the RISC type main processor. The main processor transmits YUV 4:2:2 type raw data captured by a CMOS image sensor to another processor(such as motion controller, PC, etc) via serial communication (rs232, SPI, I2C, etc). The role of another processor is line and obstacle detecting in image data received from the image processing board developed in this paper.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Korea Computer Industry Society
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• v.4 no.4
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• pp.547-552
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• 2003

In this thesis, interference phenomena of bluetooth networks requiring Security were minimized; strengthened security of piconet by assigning an identical PIN code to bluetooth devices, which was establishing a specific piconet during authentication stage. To establish a bluetooth piconet system. an unique ID was assigned to each bluetooth device, communication algorithms having different data formats between devices was designed, and an embedded hardware module using ARM processor and uCOS-II RTOS was implemented. About 30% of CPU efficiency in the module was increased by modifying functions including block parameters to work as nonblocking; by the increased efficiency of total piconet, the module could be used as an access point. The module could transmit maximum 10 frames of image and also audio signal by switching the packet effectively according to channel condition. By above-mentioned process, video, audio, and data could be well transmitted by the bluetooth managing program and the possibility of a commercial remote control system using bluetooth technology was suggested.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.21-30
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• 1990

This paper describes a hardware implementation of the interframe monochrome video CODEC using a MC-CVQ(Motion Compensated and Classified Vector Quantization) algorithm. The specifications of this CODEC are (1) the resolution of image is $128{\times}128$ pixels, and (2) the transmission rates are about 10frames/sec at the 64Kbps channel. In order to design the CODEC under these conditions, it is implemented by a multiprocessor system composed of MC unit, CVQ nuit and decoder unit, which are controlled by microprogramming technique. And the 3~stage pipelined ALU(Arithmetic and Logic Unit) is adopted to calculate the minimum error distance in the MC unit and CVQ nuit. The realized system shows that the transmission rates are 6-15 frames/sec according to the relative motion of the video signal.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.48-55
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• 2010

The goal of this paper is to determine optimal hardware platform for specific applications. In order to develop an understanding of how select the optimal platform, we focus upon the real-time embedded vehicle system for processing forward image and sound. In this paper we propose to measure parameters such as instructions, execution cycle, required memory size for program and data by using ARMulator. We have measured three types of processor cores: ARM7, ARM9 and ARM10. The results of the study indicated that the proposed methods could measure the minimal requirements of hardware platform for specific applications. By defining lower limit of hardware specifications in embedded systems, we can minimize expenses with suitable system performance without implementing the system.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.